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參數(shù)資料
| 型號： | HS9-80C85RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened 8-Bit CMOS Microprocessor |
| 中文描述： | 輻射加固8位CMOS微處理器 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 159K |
| 代理商： | HS9-80C85RH |
6
Specifications HS-80C85RH
A8-15 Valid Before Trailing Edge of ALE (Note 5)
TAL
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
75
-
ns
A0-7 Valid Before Trailing Edge of ALE
tALL
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
125
-
ns
READY Valid from Address
Valid
TARY
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
250
-
ns
Address (A8-15) Valid After Control
TCA
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
150
-
ns
Width of Control Low (RD, WR, INTA) Edge of
ALE
TCC
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
575
-
ns
Trailing Edge of Control to Leading Edge of ALE
TCL
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
60
-
ns
Data Valid to Trailing Edge of WRITE
TDW
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
575
-
ns
HLDA to Bus Enable
THABE
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
375
ns
Bus Float After HLDA
THABF
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
375
ns
HLDA Valid to Trailing Edge of CLK
THACK
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
90
-
ns
HOLD Hold Time
THDH
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
0
ns
HOLD Setup Time to Trailing Edge of CLK
THDS
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
300
ns
INTR Hold Time
TINH
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
0
ns
INTR, RST and TRAP Setup Time to Falling
Edge of CLK
TINS
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
375
ns
Address Hold Time After ALE
TLA
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
75
-
ns
Trailing Edge of ALE to Leading Edge of Control
TLC
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
150
-
ns
ALE Low During CLK High
TLCK
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
125
-
ns
ALE to Valid Data During Read
TLDR
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
675
-
ns
ALE to Valid Data During Write
TLDW
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
350
ns
ALE Width
TLL
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
200
-
ns
ALE to READY Stable
TLRY
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
175
ns
Trailing Edge of READ to Re-Enabling the Ad-
dress
TRAE
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
120
-
ns
READ (or INTA) to Valid Data
TRD
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
375
-
ns
Control Trailing Edge to Leading Edge of Next
Control
TRV
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
550
-
ns
Data Hold Time After READ INTA
TRDH
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
0
ns
READY Hold Time
TRYH
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
0
ns
READY Setup Time to Leading Edge of CLK
TRYS
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
250
-
ns
Data Valid After Trailing Edge of WRITE
TWD
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
150
-
ns
LEADING Edge of WRITE to Data Valid
TWDL
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
50
ns
NOTES:
1. Output timings are measured with a purely capacitive load, CL = 150pF
2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V
3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.
4. The AC table is tested as shown above to guarantee the processor system timing.
5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,
So, and S1 are stable.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER
SYMBOL
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Spec Number
518054
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| HS9-80C85RH/PROTO | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8-Bit CMOS Microprocessor |
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| HS9-80C86RH/PROTO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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