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參數(shù)資料
| 型號： | HS9-80C85RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened 8-Bit CMOS Microprocessor |
| 中文描述： | 輻射加固8位CMOS微處理器 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 159K |
| 代理商： | HS9-80C85RH |
16
HS-80C85RH
Basic System Timing
The HS-80C85RH has a multiplexed Data Bus. ALE is used
as a strobe to sample the lower 8-bits of address on the
Data Bus. Figure 15 shows an instruction fetch, memory
read and I/O write cycle (as would occur during processing
of the OUT instruction). Note that during the I/O write and
read cycle that the I/O port address is copied on both the
upper and lower half of the address.
There are seven possible types of machine cycles. Which of
these seven takes place is defined by the status of the three
status lines (lO/M, S1, S0) and the three control signals (RD,
WR, and INTA). (See Table 10.) The status lines can be
used as advanced controls (for device selection, for exam-
ple), since they become active at the T1 state, at the outset
of each machine cycle. Control lines RD and WR are used
as command lines since they become active when the trans-
fer of data is to take place.
TABLE 10. HS-80C85RH MACHINE CYCLE CHART
MACHINE CYCLE
STATUS
CONTROL
IO/M
S1
S0
RD WR INTA
Opcode Fetch (OF)
0
1
1
0
1
1
Memory Read (MR)
0
1
0
0
1
1
Memory Write (MW)
0
0
1
1
0
1
I/O Read
(IOR)
1
1
0
0
1
1
I/O Write
(IOW)
1
0
1
1
0
1
Acknowledge
of INTR
(INA)
1
1
1
1
1
0
Bus Idle
(BI)
DAD
Ack. of
0
1
0
1
1
1
RST,
TRAP
1
1
1
1
1
1
HALT
TS
0
0
TS
TS
1
A machine cycle normally consists of three T states, with the
exception of OPCODE FETCH, which normally has either
four or six T states (unless WAIT or HOLD states are forced
by the receipt of READY or HOLD inputs). Any T state must
be one of ten possible states, shown in Table 11.
TABLE 11. HS-80C85RH MACHINE STATE CHART
MA-
CHINE
STATE
STATUS & BUSES
CONTROL
S1, S0 IO/M
A8-15
AD0-7
RD,WR
INTA ALE
T1
X
X
X
X
1
1
1
T2
X
X
X
X
X
X
0
TWAIT
X
X
X
X
X
X
0
T3
X
X
X
X
X
X
0
T4
1
0
0
0
X
TS
1
1
0
T5
1
X
TS
1
1
0
T6
1
X
TS
1
1
0
TRESET
X
TS
TS
TS
TS
1
0
THALT
0
TS
TS
TS
TS
1
0
THOLD
X
TS
TS
TS
TS
1
0
0 = Logic “0”
1 = Logic “1”
ALE not generated during 2nd and 3rd machine cycles of DAD
instruction.
IO/M = 1 during T4, T6 of INA machine cycle.
TS = High Impedance
X = Unspecified
FIGURE 15. 80C85RH BASIC SYSTEM TIMING
M1
M3
M2
T1
T2
T3
T4
T1
T2
T3
T1
T2
T3
T
CLK
A8-A15
AD0-7
ALE
RD
WR
IO/M
STATUS
PCH (HIGH ORDER ADDRESS)
(PC + 1)H
IO PORT
IO PORT
(PC+1)L
PCL
(LOW ORDER
ADDRESS)
DATA FROM
MEMORY
(INSTRUCTION)
DATA FROM
MEMORY (I/O
PORT ADDRESS)
DATA TO
MEMORY OR
PERIPHERAL
S1-S0 (FETCH)
10 (READ)
01 WRITE
11
Spec Number
518054
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相關(guān)代理商/技術(shù)參數(shù) |
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| HS9-80C85RH/PROTO | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 8-Bit CMOS Microprocessor |
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| HS9-80C86RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 16-Bit CMOS Microprocessor |
| HS9-80C86RH/PROTO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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