參數(shù)資料
型號(hào)： HS1-80C86RH-8
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： Radiation Hardened 16-Bit CMOS Microprocessor
中文描述： 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40
封裝： SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40
文件頁(yè)數(shù)： 37/37頁(yè)
文件大小： 239K
代理商： HS1-80C86RH-8
892
Spec Number
518055
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HS-80C86RH
E
E1
D
S1
b
Q
E2
A
C
1
A
A
M
c1
b1
(c)
(b)
SECTION A-A
BASE
METAL
LEAD FINISH
M
e
N
L
K42.A
TOP BRAZED
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
SYMBOL
A
b
b1
c
c1
D
E
E1
E2
e
k
L
Q
S1
M
N
INCHES
MIN
-
0.017
0.017
0.007
0.007
1.045
0.630
-
0.530
0.050 BSC
-
0.320
0.045
0.000
-
MILLIMETERS
MIN
-
0.43
0.43
0.18
0.18
26.54
16.00
-
13.46
1.27 BSC
-
8.13
1.14
0.00
-
42
NOTES
-
-
-
-
-
3
-
3
-
11
-
-
8
6
-
-
MAX
0.100
0.025
0.023
0.013
0.010
1.075
0.650
0.680
0.550
MAX
2.54
0.64
0.58
0.33
0.25
27.31
16.51
17.27
13.97
-
-
0.350
0.065
-
0.0015
8.89
1.65
-
0.04
42
Rev. 0 6/17/94
Ceramic Metal Seal Flatpack Packages (Flatpack)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
11. The basic lead spacing is 0.050 inch (1.27mm) between center
lines. Each lead centerline shall be located within
±
0.005 inch
(0.13mm) of its exact longitudinal position relative to lead 1 and
the highest numbered (N) lead.
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