參數(shù)資料
型號(hào)： HS1-80C86RH-8
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： Radiation Hardened 16-Bit CMOS Microprocessor
中文描述： 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40
封裝： SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40
文件頁(yè)數(shù)： 33/37頁(yè)
文件大小： 239K
代理商： HS1-80C86RH-8
888
Spec Number
518055
HS-80C86RH
LOGIC
NOT = Invert
1 1 1 1 0 1 1 w
mod 0 1 0 r/m
SHL/SAL =
Shift Logical/Arithmetic Left
1 1 0 1 0 0 v w
mod 1 0 0 r/m
SHR =
Shift Logical Right
1 1 0 1 0 0 v w
mod 1 0 1 r/m
SAR =
Shift Arithmetic Right
1 1 0 1 0 0 v w
mod 1 1 1 r/m
ROL =
Rotate Left
1 1 0 1 0 0 v w
mod 0 0 0 r/m
ROR =
Rotate Right
1 1 0 1 0 0 v w
mod 0 0 1 r/m
RCL =
Rotate Through Carry Flag Left
1 1 0 1 0 0 v w
mod 0 1 0 r/m
RCR =
Rotate Through Carry Right
1 1 0 1 0 0 v w
mod 0 1 1 r/m
AND = And:
Reg./Memory and Register to Either
0 0 1 0 0 0 0 d w
mod reg r/m
Immediate to Register/Memory
1 0 0 0 0 0 0 w
mod 1 0 0 r/m
data
data if w = 1
Immediate to Accumulator
0 0 1 0 0 1 0 w
data
data if w = 1
TEST = And Function to Flags, No Result:
Register/Memory and Register
1 0 0 0 0 1 0 w
mod reg r/m
Immediate Data and Register/Memory
1 1 1 1 0 1 1 w
mod 0 0 0 r/m
data
data if w = 1
Immediate Data and Accumulator
1 0 1 0 1 0 0 w
data
data if w = 1
OR = Or:
Register/Memory and Register to Either
0 0 0 0 1 0 d w
mod reg r/m
Immediate to Register/Memory
1 0 0 0 0 0 0 w
mod 1 0 1 r/m
data
data if w = 1
Immediate to Accumulator
0 0 0 0 1 1 0 w
data
data if w = 1
XOR = Exclusive or:
Register/Memory and Register to Either
0 0 1 1 0 0 d w
mod reg r/m
Immediate to Register/Memory
1 0 0 0 0 0 0 w
mod 1 1 0 r/m
data
data if w = 1
Immediate to Accumulator
0 0 1 1 0 1 0 w
data
data if w = 1
STRING MANIPULATION
REP =
Repeat
1 1 1 1 0 0 1 z
MOVS =
Move Byte/Word
1 0 1 0 0 1 0 w
CMPS =
Compare Byte/Word
1 0 1 0 0 1 1 w
SCAS =
Scan Byte/Word
1 0 1 0 1 1 1 w
LODS =
Load Byte/Word to AL/AX
1 0 1 0 1 1 0 w
STOS =
Stor Byte/Word from AL/A
1 0 1 0 1 0 1 w
CONTROL TRANSFER
CALL = Call:
Direct Within Segment
1 1 1 0 1 0 0 0
disp-low
disp-high
Indirect Within Segment
1 1 1 1 1 1 1 1
mod 0 1 0 r/m
Direct Intersegment
1 0 0 1 1 0 1 0
offset-low
offset-high
seg-low
seg-high
Indirect Intersegment
1 1 1 1 1 1 1 1
mod 0 1 1 r/m
Instruction Set Summary
(Continued)
MNEMONIC AND DESCRIPTION
INSTRUCTION CODE
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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