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參數(shù)資料
| 型號(hào)： | HS1-54C138RH |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer |
| 中文描述： | 輻射加固3線至8線譯碼器/解復(fù)用器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 38K |
| 代理商： | HS1-54C138RH |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
5962R9582501QEC
-55
o
C to +125
o
C
MIL-PRF-38535 Level Q
16 Lead SBDIP
5962R9582501QXC
-55
o
C to +125
o
C
MIL-PRF-38535 Level Q
16 Lead Ceramic Flatpack
5962R9582501VEC
-55
o
C to +125
o
C
MIL-PRF-38535 Level V
16 Lead SBDIP
5962R9582501VXC
-55
o
C to +125
o
C
MIL-PRF-38535 Level V
16 Lead Ceramic Flatpack
HS1-54C138RH/SAMPLE
+25
o
C
Sample
16 Lead SBDIP
HS9-54C138RH/SAMPLE
+25
o
C
Sample
16 Lead Ceramic Flatpack
HS-54C138RH
Radiation Hardened
3-Line to 8-Line Decoder/Demultiplexer
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A
B
C
G2A
G2B
G1
GND
Y7
VDD
Y1
Y2
Y3
Y4
Y5
Y6
Y0
A
B
C
G2A
G2B
G1
Y7
GND
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Features
Devices QML Qualified in Accordance With
MIL-PRF-38535
Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95825 and Intersil’ QM Plan
Radiation Hardened EPI-CMOS
- Total Dose 1 x 10
5
RAD (Si)
- Latch-Up Immune > 1 x 10
12
RAD (Si)/s
Multiple Input Enable for Easy Expansion
Single Power Supply +5V
Outputs Active Low
Low Standby Power (0.5mW Max at +5V)
High Noise Immunity
Equivalent to Sandia SA2995
Bus Compatible with Intersil Rad-Hard 80C85RH
Full Military Temperature Range -55
o
C to +125
o
C
Description
The Intersil HS-54C138RH is a radiation hardened 3- to 8-line
decoder fabricated using a radiation hardened EPI-CMOS pro-
cess. It features low power consumption, high noise immunity,
and high speed. Also featured are pin and function compatibility
with the 54LS138 industry standard part. The HS-54C138RH is
ideally suited for high speed memory chip select address
decoding. It is intended for use with the Intersil HS-80C85RH
radiation hardened microprocessor, but it can also be utilized as
a demultiplexer in any low power rad-hard application.
The HS-54C138RH contains a one of eight binary decoder.
A three bit binary input is used to select and activate each of
the eight outputs, provided the three chip enable inputs are
also present (see truth table).
The HS-54C138RH has an on-chip enable gate. The active
high (G1) and both active low (G2A, G2B) inputs are Anded
together to provide a single enable input to the device. The
use of both active high and active low inputs minimizes the
need for external gates when expanding a system.
February 1996
Spec Number
518053
File Number
3037.2
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