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參數(shù)資料
| 型號： | HS1-2420RH-Q |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 運動控制電子 |
| 英文描述： | Radiation Hardened Fast Sample and Hold |
| 中文描述： | SAMPLE AND HOLD AMPLIFIER, CDIP14 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 122K |
| 代理商： | HS1-2420RH-Q |
10
HS-2420RH
Offset and Gain Adjustment
Offset Adjustment
The offset voltage of the HS-2420RH may be adjusted using
a 100k
trim pot, as shown in Figure 15. The recommended
adjustment procedure is:
1. Apply zero volts to the sample-and-hold input, and a
square wave to the S/H control.
2. Adjust the trim pot for zero volts output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain
error at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a -10V
output.
5. Measure the output hold voltage (V-10 NOMINAL). Adjust
the trim pot for an output hold voltage of
--------------------------------------------------+
)
Spec Number
518855
FIGURE 14. HOLD STEP vs INPUT VOLTAGE
FIGURE 15. BASIC SAMPLE-AND-HOLD (TOP VIEW)
FIGURE 16. INVERTING CONFIGURATION
FIGURE 17. NONINVERTING CONFIGURATION
+10
+5
-5
-10
-15
-20
-25
-30
-35
-10
-5
+5
+10
DC INPUT VOLTAGE (V)
HOLD STEP VOLTAGE (V)
CH = 0.1
μ
F
CH = 10,000pF
CH = 1000pF
CH = 100pF
+IN
V-
100k
OFFSET TRIM
(
±
25mV RANGE)
OUT
-IN
V+
CH
S/H
CONTROL
-
+
-
+
HS-2420RH
-IN
+IN
OUT
S/H
CONTROL
INPUT
RI
OUTPUT
0.002RF
RF
S/H CONTROL
INPUT
HS-2420RH
GAIN
~
-RF
RI
+IN
-IN
OUT
S/H
CONTROL
INPUT
RI
OUTPUT
0.002RI
RF
S/H CONTROL
INPUT
HS-2420RH
GAIN
~ I +
-RF
RI
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