參數(shù)資料
型號: HN58V256A
廠商: Hitachi,Ltd.
英文描述: 256k EEPROM (32-kword x 8-bit) Ready/Busy and RES function (HN58V257A)
中文描述: 256k的EEPROM(32 KWord的× 8位)就緒/忙和RES功能(HN58V257A)
文件頁數(shù): 7/24頁
文件大小: 118K
代理商: HN58V256A
HN58V256A Series, HN58V257A Series
7
Write Cycle
Parameter
Symbol
Min*
3
Typ
Max
Unit
Test conditions
Address setup time
t
AS
t
AH
t
CS
t
CH
t
WS
t
WH
t
OES
t
OEH
t
DS
t
DH
t
WP
t
CW
t
DL
t
BLC
t
BL
t
WC
t
DB
t
DW
t
RP
t
RES
0
ns
Address hold time
CE
to write setup time (
WE
controlled)
CE
hold time (
WE
controlled)
WE
to write setup time (
CE
controlled)
WE
hold time (
CE
controlled)
OE
to write setup time
OE
hold time
50
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
Data setup time
70
ns
Data hold time
WE
pulse width (
WE
controlled)
CE
pulse width (
CE
controlled)
0
ns
200
ns
200
ns
Data latch time
100
ns
Byte load cycle
0.3
30
μ
s
μ
s
Byte load window
100
Write cycle time
10*
4
ms
Time to device busy
120
ns
Write start time
0*
5
ns
Reset protect time*
2
100
μ
s
μ
s
Reset high time*
2, 6
Notes: 1. t
and t
are defined as the time at which the outputs achieve the open circuit conditions and are
no longer driven.
2. This function is supported by only the HN58V257A series.
3. Use this device in longer cycle than this value.
4. t
must be longer than this value unless polling techniques or RDY/
Busy
(only the HN58V257A
series) are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
(only the
HN58V257A series) are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
WE
.
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of
CE
.
9. See AC read characteristics.
1
相關(guān)PDF資料
PDF描述
HN58V256AFP-12 256k EEPROM (32-kword x 8-bit) Ready/Busy and RES function (HN58V257A)
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