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參數(shù)資料
| 型號(hào)： | HMS87C1302AD |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 54/70頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HMS87C1302AD |
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HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
54
Preliminary
Jan. 2001
15.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6
H
) as shown in Figure 15-6 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
Figure 15-6 External Interrupt Block Diagram
Example: To use as an INT0 and INT1
:
:
;
**** Set port as an input port RB2
LDM
;
;
**** Set port as an interrupt port
LDM
;
;
**** Set Falling-edge Detection
LDM
:
:
:
RBIO,#1111_1011B
RBFUNC,#04H
IEDS,#0000_0001B
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
shows interrupt response timings.
Figure 15-7 Interrupt Response Timing Diagram
INT0IF
INT0 pin
INT0 INTERRUPT
INT1IF
Preimnary
INT1 pin
INT1 INTERRUPT
IEDS
[0E6
H
]
e
INT0 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
Ext. Interrupt Edge Selection
Register
W
IEDS
ADDRESS : 0E6
RESET VALUE : 00000000
W
W
W
00 : Int. disable
01 : falling
10 : rising
11 : both
W
W
W
INT1 edge select
W
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
8 f
OSC
max. 12 f
OSC
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