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參數(shù)資料
| 型號： | HMS81008E |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | Hynix半導體公司的8位單芯片微控制器 |
| 文件頁數(shù)： | 51/77頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | HMS81008E |
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HMS81004E/08E/16E/24E/32E
48
JUNE 2001 Ver 1.00
14.1 Interrupt priority and sources
Each interrupt vector is independent and has its own pri-
ority. Software interrupt (BRK) is also available. Interrupt
source classification is shown in Table 14-1.
14.2 Interrupt control register
I flag of PSW is a interrupt mask enable flag. When I flag
= “0”, all interrupts become disable. When I flag = “1”, in-
terrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When
interrupt is occured, interrupt request flag is set, and Inter-
rupt request is detected at the edge of interrupt signal. The
accepted interrupt request flag is automatically cleared
during interrupt cycle process. The interrupt request flag
maintains “1” until the interrupt is accepted or is cleared in
program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to “0”. It is possible to read the
state of interrupt register and to mainpulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt)
Reset/Interrupt
Symbol
Priority
Hardware Reset
RESET
-
Key Scan
KSCNR
1
External Interrupt1
INT1R
2
External Interrupt2
INT2R
3
Timer0
T0R
4
Timer1
T1R
5
Timer2
T2R
6
Watch Dog Timer
WDTR
7
Basic Interval Timer
BITR
8
BRK Instruction
BRK
-
Table 14-1 Interrupt Source
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