參數(shù)資料
型號: HMS30C7080
廠商: Electronic Theatre Controls, Inc.
英文描述: Mobile Phone Camera Back-End Processor
中文描述: 手機相機后端處理器
文件頁數(shù): 76/161頁
文件大?。?/td> 973K
代理商: HMS30C7080
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
76
7
0
Reserved
6
RW
0
1 = RX frame cut due to bus busy & excessive incoming frames
5
RW
0
1 = RX frame dropped due to no buffer assigned.
4
RW
0
1 = RX completed.
3
RW
0
1 = SYS RX FIFO overflow
2
RW
0
1 = SYS RX FIFO underflow
1
RW
0
1 = MAC RX FIFO overflow
0
RW
0
1 = MAC RX FIFO underflow
2.6.2.3.
INT_ENABLE (offset = 0x08)
Each bit of this register can be set to enable corresponding interrupt source. Writing ‘0’ disables the
source from generating interrupt.
Table 2.25 Interrupt Enable Bit Definition
MAC0 Address :
1920_0008
MAC1 Address :
1920_1008
Bits
Access Default Description
31
RW
0
MII PHY
0 = Interrupt disabled
1 = Interrupt enabled
This bit will be set whenever PHY device sends an interrupt
30
RW
0
MII Scan
0 = Interrupt disabled
1 = Interrupt enabled
This bit will be set when single read is completed in scan mode. Refer to
MII_CMD register (offset = 0x34).
29
RW
0
TX error occurred at PHY
0 = Interrupt disabled
1 = Interrupt enabled
28
RW
0
RX error occurred at PHY
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