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參數(shù)資料
| 型號： | HMP8154 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Encoders |
| 中文描述： | 的NTSC / PAL編碼器 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大?。?/td> | 256K |
| 代理商： | HMP8154 |
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27
Output Compliance Range
0
-
1.4
V
Video Level Error
Internal Voltage Reference
(Note 4)
VREF unconnected, RSET = 133
-
-
±
10
%
External Voltage Reference
VREF = 1.230V (Figure 37), RSET = 140
-
-
±
10
%
DAC to DAC Matching
-
-
5
%
VREF Output Voltage
Pin not driven, using internal reference
1.13
1.195
1.32
V
VREF Output Current
-50
-
50
μ
A
VREF Input Voltage
Pin connected to external reference shown in
Figure 37.
1.112
1.230
1.358
V
VREF Input Current
-500
-
500
μ
A
AC PARAMETERS, ANALOG OUTPUTS
Differential Gain Error
Using analog output filter shown in Figure 38A.
-
1
-
%
Differential Phase Error
-
1
-
Degree
SNR (Weighted)
-
70
-
dB
Hue Accuracy
-
2
-
Degree
Color Saturation Accuracy
-
2
-
%
Luminance Nonlinearity
-
1
-
%
Residual Subcarrier
-
-60
-
dB
SCH Phase
SCH Phase Reset enabled
-
±
1.5
-
Degree
Analog Output Skew, T
ASK
Analog Output Delay, T
AD
DAC-DAC Crosstalk
-
-
3
ns
-
-
12
ns
-
-60
-
dB
Glitch Energy
Using analog output filter shown in Figure 38A.
Includes clock and data feedthrough
-
35
-
pV-s
AC PARAMETERS, DIGITAL INPUTS AND OUTPUTS EXCEPT SCL AND SDA
Setup Time, T
S
Hold Time, T
H
CLK2 Frequency
8
-
-
ns
0
-
-
ns
-
-
30.0
MHz
CLK2 High Time, CLK2
H
CLK2 Low Time, CLK2
L
CLK2 to Output Delay, T
D
RESET* Pulse Width Low, T
RES
13.6
-
20.3
ns
13.6
-
20.3
ns
2
-
12
ns
4
-
-
CLK
Cycles
AC PARAMETERS, SCL AND SDA (I
2
C INTERFACE)
All AC parameters meet the fast-mode I
2
C Bus Interface specification.
POWER SUPPLY CHARACTERISTICS
DAC PSRR at DC
Note 6
-
64
-
dB
Power Supply Range, V
AA
Normal Supply Current, I
AA
Power-Down Supply Current, I
AA
Power Dissipation
4.75
5.0
5.25
V
-
-
260
mA
Note 5
-
-
750
μ
A
-
1100
1300
mW
NOTES:
4. Output level is dependent on the voltage on VREF, the value of RSET, and the load.
5. If using an external voltage reference, it is not powered down. The internal voltage reference is always powered down.
6. The supply voltage rejection is the relative variation of the full-scale output driving a 37.5
load for a
±
0.5% supply variation:
PSRR = 20 x log (
V
AA
/
V
OUT
).
Electrical Specifications
V
AA
= +5V
±
5%, RSET = 133
, VREF Unconnected, T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
HMP8154, HMP8156A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMP8154CN | NTSC/PAL Encoders |
| HMP8156A | NTSC/PAL Encoders |
| HMP8154EVAL1 | NTSC/PAL Encoders |
| HMP8190 | NTSC/PAL Video Encoder |
| HMP8190CN | NTSC/PAL Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8154_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8154EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoder |
| HMP8156_03 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoder |
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