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參數資料
| 型號： | HMP8112ACN |
| 廠商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數： | 17/40頁 |
| 文件大?。?/td> | 563K |
| 代理商： | HMP8112ACN |
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17
9 - 8
Horizontal AGC
Pulse Programmable
Start Time
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The start time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
11
B
TABLE 16. HORIZONTAL AGC END TIME REGISTER
DESTINATION ADDRESS = 0A
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Horizontal AGC
Pulse Programmable
End Time
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the lower byte
of the 10-bit word.
0000 0000
B
TABLE 17. HORIZONTAL AGC END TIME REGISTER
DESTINATION ADDRESS = 0B
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
XXXX XX
9 - 8
Horizontal AGC
Pulse Programmable
End Time
This register provides a programmable delay for the HAGC pulse that control the sync
tip AGC in the A/D converters. The end time of the HAGC pulse is set from the detection
of horizontal sync in the video data. HAGC is programmable in CLK increments and has
a fixed 1 clock delay following the falling edge of horizontal sync. This is the upper byte
of the 10-bit word.
00
B
TABLE 18. HORIZONTAL SYNC START TIME REGISTER
DESTINATION ADDRESS = 0C
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7 - 0
Horizontal Drive
Programmable Start
Time
This register provides a programmable delay for the external HDRIVE signal. The start
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the lower byte of the 10-bit word.
0011 1011
B
TABLE 19. HORIZONTAL SYNC START TIME REGISTER
DESTINATION ADDRESS = 0D
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
15 - 10
Not Used
Write Ignored, Read 0’s
XXXX XX
9 - 8
Horizontal Drive
Programmable Start
Time
This register provides a programmable delay for the external HDRIVE signal. The start
time of the HDRIVE pulse is set from the detection of horizontal sync in the video data.
HDRIVE is programmable in CLK increments and has a fixed 1 clock delay following the
falling edge of horizontal sync. This is the upper byte of the 10-bit word.
11
B
TABLE 15. HORIZONTAL AGC START TIME REGISTER (Continued)
DESTINATION ADDRESS = 09
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
HMP8112
相關PDF資料 |
PDF描述 |
|---|---|
| HMP8112CN | NTSC/PAL Video Decoder |
| HMP8112EVAL2 | NTSC/PAL Video Decoder |
| HMP8156EVAL2 | NTSC/PAL Video Decoder |
| HMP8156EVAL1 | NTSC/PAL Encoders |
| HMP8156EVAL2 | NTSC/PAL Encoders |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HMP8112CN | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:NTSC/PAL Video Decoder |
| HMP8112EVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8112EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8115 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8115CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
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