- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370636 > HM62W8512B (Hitachi,Ltd.) 4 M SRAM (512-kword ×8-bit)(4 M 靜態(tài)RAM(512k字×8位)) PDF資料下載
參數(shù)資料
| 型號： | HM62W8512B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (512-kword ×8-bit)(4 M 靜態(tài)RAM(512k字×8位)) |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位）（4個M靜態(tài)隨機存儲器（為512k字× 8位）） |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 81K |
| 代理商： | HM62W8512B |
HM62W8512B Series
7
AC Characteristics
(Ta = –20 to +70
°
C, V
CC
= 3.3 V
±
0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 0.8 V/2.0 V
Output load (Including scope & jig)
Dout
500
1.4 V
50 pF
Read Cycle
HM62W8512B
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
55
—
70
—
ns
Address access time
—
55
—
70
ns
Chip select access time
—
55
—
70
ns
Output enable to output valid
—
25
—
35
ns
Chip selection to output in low-Z
10
—
10
—
ns
2
Output enable to output in low-Z
5
—
5
—
ns
2
Chip deselection to output in high-Z
0
20
0
30
ns
1, 2
Output disable to output in high-Z
0
20
0
30
ns
1, 2
Output hold from address change
10
—
10
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM63921JP-20R | 2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921JP-25 | 2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921JP-35 | 2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921 | 560KBITS BRAM 400000 SYSTEM GATES 404 - - NOT RECOMMENDED for NEW DESIGN |
| HM63921P-20R | 560KBITS BRAM 400000 SYSTEM GATES 404 I/ - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62W8512BLFP-5 | 制造商:HITACHI 功能描述: |
| HM62W8512BLTTI7 | 制造商:Hitachi 功能描述: |
| HM-630 | 制造商:Black Box Corporation 功能描述:FACE PLATE:HM-STAINLESS |
| HM63021FP | 制造商:Panasonic Industrial Company 功能描述:IC |
| HM63021P-28 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field/Frame/Line Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。