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參數(shù)資料
| 型號(hào)： | HM62W8511H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (512-kword ×8-bit)(4M高速靜態(tài)RAM(512k字 ×8位)) |
| 中文描述： | 4分高速SRAM（512 - KWord的× 8位）（4分高速靜態(tài)隨機(jī)存儲(chǔ)器（為512k字× 8位）） |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | HM62W8511H |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)
HM62W8511H Series
14
Revision Record
Rev.
0.0
Date
Feb. 27, 1997
Contents of Modification
Initial issue
Drawn by
Y. Saitoh
Approved by
A.Ide
0.1
Nov. 20, 1997
Change of subtitle
K. Makuta
K. Makuta
0.2
Dec. 5, 1997
Features
Addition of Operating current
Addition of TTL standby current
Addition of CMOS standby current
Addition of Data retention current
Addition of Data retention voltage
Change of Block Diagram
Absolute Maximum Ratings
Change of notes
Recommended DC Operating Conditions
V
IH
: V
+ 0.3 V to V
CC
+ 0.5 V
V
: –0.3 V to –0.5 V
Change of notes
DC Characteristics
I
CC
(max): 240/200/190 mA to 170/150/130 mA
I
SB
(max): 100/100/100 mA to 60/50/40 mA
I
(max): 10/0.5 mA to 5/1 mA
Test conditions I
CC
and I
: Addition of Min cycle
Test conditions I
SB1
: Addition of f = 0 MHz
AC Characteristics
Change of Output load (A) and Output load (B)
t
OE
, t
CHZ
and t
OHZ
(max): 5/6/8 ns to 5/6/7 ns
t
AW
, t
and t
(min): 6/8/10 ns to 7/8/10 ns
t
DW
(min): 5/6/8 ns to 5/6/7 ns
t
and t
(max): 5/6/8 ns to 5/6/7 ns
Low V
CC
Data Retention Characteristics
I
: —/2/300
μ
A to —/—/300
μ
A
Change of Low V
CC
Data Retention Timing
Waveform
T. Fukazawa
K. Makuta
0.3
May. 15, 1998
Features
Change of TTL standby current
Change of Block Diagram
DC Characteristics
I
SB
(max): 60/50/40 mA to 70/60/50 mA
Delete of HM62W8511H-10 Series
Features
Change of Data retention current
DC Characteristics
I
(typ): —/— mA to 0.05/0.05 mA
Low V
CC
Data Retention Characteristics
I
CCDR
: —/—/300
μ
A to —/40/600
μ
A
T. Fukazawa
K. Makuta
1.0
Sep. 15, 1998
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