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參數(shù)資料
| 型號(hào)： | HM62W8511H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (512-kword ×8-bit)(4M高速靜態(tài)RAM(512k字 ×8位)) |
| 中文描述： | 4分高速SRAM（512 - KWord的× 8位）（4分高速靜態(tài)隨機(jī)存儲(chǔ)器（為512k字× 8位）） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 107K |
| 代理商： | HM62W8511H |
HM62W8511H Series
4M High Speed SRAM (512-kword
×
8-bit)
ADE-203-750D (Z)
Rev. 1.0
Sept. 15, 1998
Description
The HM62W8511H is a 4-Mbit high speed static RAM organized 512-kword
×
8-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. The
HM62W8511H is packaged in 400-mil 36-pin SOJ for high density surface mounting.
Features
Single supply : 3.3 V
±
0.3 V
Access time 12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current : 150/130 mA (max)
TTL standby current : 60/50 mA (max)
CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
Data retention current : 0.6 mA (max) (L-version)
Data retention voltage : 2 V (min) (L-version)
Center V
CC
and V
SS
type pinout
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| HM62W8512BLFP-5 | 制造商:HITACHI 功能描述: |
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