參數(shù)資料
型號(hào): HM62W16258BI
廠商: Hitachi,Ltd.
英文描述: 4 M SRAM (256-kword ×16-bit)(4 M 靜態(tài)RAM(256k字×16位))
中文描述: 四米的SRAM(256 - KWord的× 16位)(4個(gè)M靜態(tài)隨機(jī)存儲(chǔ)器(256k字× 16位))
文件頁(yè)數(shù): 6/14頁(yè)
文件大?。?/td> 347K
代理商: HM62W16258BI
HM62W16258BI Series
6
Write Cycle
Notes: 1. t
CHZ
, t
OHZ
, t
WHZ
and t
BHZ
are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given
device and from device to device.
4. A write occures during the overlap of a low CS, a low WE and a low LB or a low UB. A write
begins at the latest transition among CS going low, WE going low and LB going low or UB going
low. A write ends at the earliest transition among CS going high, WE going high and LB going
high or UB going high. t
WP
is measured from the beginning of write to the end of write.
5. t
CW
is measured from the later of CS going low to the end of write.
6. t
AS
is measured from the address valid to the beginning of write.
7. t
WR
is measured from the earliest of CS or WE going high to the end of write cycle.
Parameter
Write cycle time
Address valid to end of write
Chip selection to end of write
Write pulse width
LB, UB valid to end of write
Address setup time
Write recovery time
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in High-Z
Write to output in high-Z
Symbol
t
WC
t
AW
t
CW
t
WP
t
BW
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
HM62W16258BI
-7
Min
70
60
60
50
55
0
0
30
0
5
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Max
25
25
5
4
6
7
2
1, 2
1, 2
相關(guān)PDF資料
PDF描述
HM62W16258BLTT-5 4 M SRAM (256-kword x 16-bit)
HM62W16258B 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-5SL 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-7 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-7SL 4 M SRAM (256-kword x 16-bit)
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