參數(shù)資料
型號(hào)： HM62W16258BI
廠商： Hitachi,Ltd.
英文描述： 4 M SRAM (256-kword ×16-bit)(4 M 靜態(tài)RAM(256k字×16位))
中文描述： 四米的SRAM（256 - KWord的× 16位）（4個(gè)M靜態(tài)隨機(jī)存儲(chǔ)器（256k字× 16位））
文件頁(yè)數(shù)： 10/14頁(yè)
文件大?。?/td> 347K
代理商： HM62W16258BI
HM62W16258BI Series
10
Write Cycle (3) (LB, UB Clock, OE = V
IH
)
Low V
CC
Data Retention Characteristics (Ta =
–40 to +85
°
C)
Notes: 1. 10
μ
A max. at Ta = 0 to +40
°
C.
2. CS controls address buffer, WE buffer, OE buffer, LB, UB buffer and Din buffer. If CS controls
data retention mode, Vin levels (address, WE, OE, LB, UB, I/O) can be in the high impedance
state. If LB, UB controls data retention mode, LB, UB must be LB = UB
≥
V
CC
– 0.2 V, CS must
be CS
≤
0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state.
3. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and not guaranteed.
4. t
RC
= read cycle time.
Parameter
V
CC
for data retention
Symbol
V
DR
Min
2.0
Typ*
3
Max
—
Unit
V
Test conditions
*2
Vin
≥
0V
(1)CS
≥
V
CC
– 0.2 V or
(2)LB = UB
≥
V
CC
– 0.2 V
CS
≤
0.2 V
V
CC
= 3.0 V, Vin
≥
0V
(1)CS
≥
V
CC
– 0.2 V or
(2)LB = UB
≥
V
CC
– 0.2 V
CS
≤
0.2 V
See retention waveform
—
Data retention current
I
CCDR*1
—
0.8
20
μ
A
Chip deselect to data
retention time
Operation recovery time
t
CDR
0
—
—
ns
t
R
t
RC*4
—
—
ns
Address
WE
t
WC
t
AW
t
WP
*
4
t
CW
*
5
t
BW
t
WR
*
7
t
DW
t
DH
Valid address
Valid data
LB
,
UB
Dout
Din
High impedance
CS
t
AS
*
6
相關(guān)PDF資料
PDF描述
HM62W16258BLTT-5 4 M SRAM (256-kword x 16-bit)
HM62W16258B 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-5SL 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-7 4 M SRAM (256-kword x 16-bit)
HM62W16258BLTT-7SL 4 M SRAM (256-kword x 16-bit)
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