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參數(shù)資料
| 型號： | HM628512BI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (512-kword ×8-bit)(4M靜態(tài)RAM (512k字 ×8位)) |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位）（4分靜態(tài)隨機存儲器（為512k字× 8位）） |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 86K |
| 代理商： | HM628512BI |
HM628512BI Series
6
Write Cycle
Notes:
1.t
HZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open
circuit\~conditions and are not referred to output voltage levels.
2.This parameter is sampled and not 100% tested.
3.A write occurs during the overlap (t
WP
) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going
high or WE going high. t
WP
is measured from the beginning of write to the end of write.
4.t
CW
is measured from CS going low to the end of write.
5.t
AS
is measured from the address valid to the beginning of write.
6.t
WR
is measured from the earlier of WE or CS going high to the end of write cycle.
7.During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8.If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output remain in a high impedance state.
9.Dout is the same phase of the write data of this write cycle.
10.Dout is the read data of next address.
11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12.In the write cycle with OE low fixed, t
WP
must satisfy the following equation to avoid a
problem of data bus contention. t
WP
≥
t
DW
min + t
WHZ
max
HM628512BI
-7
Min
70
60
0
60
50
0
0
30
0
5
0
-8
Min
85
75
0
75
55
0
0
35
0
5
0
Parameter
Write cycle time
Chip selection to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time
WE to output in high-Z
Data to write time overlap
Data hold from write time
Output active from output in high-Z
Output disable to output in high-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
Max
—
—
—
—
—
—
25
—
—
—
25
Max
—
—
—
—
—
—
30
—
—
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
5
3, 12
6
1, 2, 7
2
1, 2, 7
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| HM628512CLTT-5 | 4 M SRAM (512-kword x 8-bit) |
| HM628512C | Octal Buffers And Line Drivers With 3-State Outputs 20-CFP -55 to 125 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM628512BISERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HM628512BLFP-5 | 制造商:Hitachi 功能描述:Static RAM, 512Kx8, 32 Pin, Plastic, SOP |
| HM628512BLFP-5SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
| HM628512BLFP-5UL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M SRAM (512-kword x 8-bit) |
| HM628512BLFP7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-SM-4MB CMOS SRAM |
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