參數(shù)資料
型號: HM624256A
廠商: Hitachi,Ltd.
英文描述: 262144-word ×4-bit High Speed CMOS Static RAM(262144字 ×4位高速CMOS SRAM)
中文描述: 262144字× 4位高速CMOS靜態(tài)RAM(262144字× 4位高速CMOS SRAM的)
文件頁數(shù): 8/12頁
文件大小: 87K
代理商: HM624256A
HM624256A Series
8
Read Timing Waveform (3)
*1, *2
(
WE
= V
IH
,
OE
= V
IL
)
t
ACS
t
CLZ
t
PU
50 %
50 %
t
PD
t
CHZ
High
Impedance
High Impedance
I
I
CC
SB
CS
Dout
V supply
current
Valid Data
Notes:
1.
Transition is measured
±
200 mV from steady state voltage with Load (B). This parameter is
sampled and not 100% tested.
Device is continuously selected,
CS
= V
IL
.
2.
Write Cycle
HM624256A-20
HM624256A-25
HM624256A-35
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Write cycle time
t
WC
20
25
35
ns
Chip selection to end of write
t
CW
15
17
25
ns
Address valid to end of write
t
AW
16
20
30
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
*2
15
17
25
ns
Write recovery time
t
WR
*3
0
0
0
ns
Output disable to output in high-Z
t
OHZ
*4
0
10
0
10
0
10
ns
Write to output in high-Z
t
WHZ
*4
0
12
0
15
0
15
ns
Data to write time overlap
t
DW
12
15
20
ns
Data hold from write time
t
DH
*5
0
0
0
ns
Output active from end of write
Notes: 1. Transition is measured
±
200 mV from steady state voltage with Load (B). This parameter is
sampled and not 100% tested.
2. A write occurs during the overlap (t
WP
) of a low
CS
and a low
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If
CS
is low during this period, I/O pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
t
OW
*1
0
0
0
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM624256AJP-20 制造商:Hitachi 功能描述: 制造商:Hitachi 功能描述:Static RAM, 256Kx4, 28 Pin, Plastic, SOJ
HM624256AJP25T 制造商:HITACHI 功能描述:New
HM624256ALJP20 制造商:HITCHI 功能描述:
HM624256ALP-20 制造商:Hitachi 功能描述:
HM624256JP-35 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM