參數(shù)資料
型號(hào): HM10S604
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 顯示驅(qū)動(dòng)器
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, UUC
封裝: TCP
文件頁(yè)數(shù): 14/16頁(yè)
文件大小: 249K
代理商: HM10S604
CONFIDENT IAL & PROPRIET ARY
HM10S604 PRELIMINARY SPEC
Timing requirements over recommended operating free air temperature range.
VDD1 = 2.7V to 3.6V
Parameter
DCLK cycle time
- See Fig 3.
Test Conditions
ns
Unit
14
MIN TYP MAX
High level DCLK pulse width duration
ns
2.0
Low level DCLK pulse width duration
ns
2.0
Data/REV setup time
ns
2.0
Data/REV hold time
ns
0
Start pulse setup time
ns
2.0
Start pulse hold time
ns
0
Start pulse signal delay time ( Load = 25pF)
ns
10
td2
5
td3
8
LCD drive signal delay time
LOAD signal EIO(input) setup time
DCLK cycle
2
LOAD low hold time from final data DCLK
DCLK cycle
1
High level LOAD signal pulse width duration
2
POLC signal LOAD setup time
ns
-5
POLC signal LOAD hold time
ns
6.0
- See Fig 3.
- See Fig 3.
- See Fig 3.
- See Fig 3.
- See Fig 3.
- See Fig 3.
- See Fig 3
- See Fig 4.note7,9
- See Fig 4.note8,9
- See Fig 4.
- See Fig 4.
- See Fig 4.
- See Fig 4.
- See Fig 4.
Fig 2. Load conditions of analog output pin.
The values of R and C could be changed according to the situation.
R = 1k
C = 15pF
Measured Point
O
R
C
R
C
R
C
R
C
R
C
tc1
tw1
tw2
tsu1
th1
tsu2
th2
td1
tsu3
th3
tw3
tsu4
th4
DCLK cycle
Output high impedance duration
66
- See Fig 4.note 10
thiz
DCLK cycle
tw3+3 DCLK cycle
- See Fig 5.note 11
-
Notes : 7. Specified as the value at which the driver’s output voltage reaches the target output voltage (VDD2X0.1).
8. Specified as the value at which ther driver’s output voltage reaches the target output voltage(6-bit precision)
9. The load of the analog output terminal is the value shown in Fig 2.
10. When LOAD high level pulse width duration is shorter than 63 DCLK cycle, high-Z duration is 66 DCLK cycle.
11. When LOAD high level pulse width duration is longer than 63 DCLK cycle, high-Z duration is tw3+3DCLK cycle.
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