參數(shù)資料
型號(hào): HM-6551B883
廠商: Intersil Corporation
英文描述: 256 x 4 CMOS RAM
中文描述: 256 × 4 CMOS存儲(chǔ)器
文件頁(yè)數(shù): 2/9頁(yè)
文件大?。?/td> 116K
代理商: HM-6551B883
6-102
Functional Diagram
NOTES:
1. Select Latch: L Low
Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high
output active.
5. Data Latches: L High
Q = D and Q latches on falling edge of L.
GATED
ROW
DECODER
A0
A1
A5
A6
A7
32
5
5
A
A
LATCHED
ADDRESS
REGISTER
32 x 32
MATRIX
D
3
3
A
A
S1
S2
W
E
LATCH
SELECT
A4
A3
A2
LATCHED ADDRESS
REGISTER
LATCHES
DATA
OUTPUT
GATED COLUMN
DECODER
AND DATA I/O
D0
A
A
A
A
A
A
A
A
L
8
8
8
8
D
D
D
D1
D2
D3
D
Q
L
Q
Q
Q
Q
Q0
Q1
Q2
Q3
HM-6551/883
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