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6-101
March 1997
HM-6551/883
256 x 4 CMOS RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Low Power Standby. . . . . . . . . . . . . . . . . . . . 50
μ
W Max
Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
Fast Access Time. . . . . . . . . . . . . . . . . . . . . .220ns Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
TTL Compatible Input/Output
High Output Drive - 1 TTL Load
Internal Latched Chip Select
High Noise Immunity
On-Chip Address Register
Latched Outputs
Three-State Output
Description
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
PACKAGE
TEMPERATURE RANGE
-55
o
C to +125
o
C
220ns
300ns
PKG. NO.
CERDIP
HM-6551B/883
HM1-6551/883
F22.4
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
S
Chip Select
D
Data Input
Q
Data Output
1
22
12
13
14
15
16
17
18
19
21
20
11
10
9
8
7
6
5
3
2
A2
A1
A0
A5
A6
A7
D0
GND
Q0
D1
A4
Q3
D3
Q2
D2
Q1
4
A3
VCC
W
S1
E
S2
File Number
2988.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright
Intersil Corporation 1999