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參數(shù)資料
| 型號： | HL14203 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | Hyundai Electronics Industries System IC Division |
| 中文描述： | 現(xiàn)代電子工業(yè)系統(tǒng)集成電路部 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 421K |
| 代理商： | HL14203 |
21
HL14203
P r e l i m i n a r y
Absolute
Maximum
Rating at Ta=25
é
, Vss = 0V
13. Electrical Characteristics
Parameter
Symbol
VDD max
Vin1
Vin2
Vout1
Condition
Maximum supply voltage
VDD
CE,SCK,SI
OSC,KIN1 to KIN5, TEST,VCL1,2
SO
OSC, SEG1 to SEG42, COM1 to
COM3, KS1 to KS6, P1 to P4
SEG1 to SEG42
COM1 to COM3
KS1 to KS6
P1 to P4
Ta = 85
é
Rating
-0.3 to +7.0
-0.3 to +7.0
-0.3 to VDD+0.3
-0.3 to +7.0
unit
V
V
V
V
Input voltage
Output voltage
Vout2
-0.3 to VDD+0.3
V
Output current
Iout1
Iout2
Iout3
Iout4
Pd max
Topr
Tstg
300
uA
mA
mA
mA
mW
é
é
3
1
5
Allowable power dissipation
Operating temperature
Storage temperature
200
-40 to +85
-55 to +125
Recommend operating ranges at Ta= -40
é
to +85
é
, Vss = 0V
Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and
load capacitance CL .
Parameter
Symbol
VDD
VCL1
VCL2
VIH1
VIH2
VIL
Condition
Supply voltage
unit
V
V
V
V
V
V
Input voltage
Input high level voltage
pF
COSC
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High level clock pulse width
Low level clock pulse width
Rise time
Fall time
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input low level voltage
Recommended external
capacitance
SO output delay time
SO rise time
fOSC
tds
tdh
tcp
tcs
tch
t0H
toL
tr
tf
tdc
tdr
max
6.0
VDD
VDD
6.0
VDD
0.2VDD
TBD
typ
2/3VDD
1/3VDD
TBD
38
min
4.5
0.8VDD
0.6VDD
TBD
160
160
160
160
160
160
160
0
VDD
VCL1
VCL2
CE,SCK,SI
KIN1 to KIN5
CE,SCK,SI,KIN1 to KIN5
OSC
SO,RPU = 4.7k
,
CL = 10pF*1
SO,RPU = 4.7k
,
CL = 10pF*1
OSC
SCK,SI
SCK,SI
CE,SCK
CE,SCK
CE,SCK
SCK
SCK
CE,SCK,SI
CE,SCK,SI
160
160
μs
1.5
μs
1.5
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