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參數(shù)資料
| 型號： | HIP7030A0 |
| 廠商： | Intersil Corporation |
| 英文描述： | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| 中文描述： | J1850 8位微控制器仿真器68HC05的版本 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 44K |
| 代理商： | HIP7030A0 |
9-41
HIP7030A0
Block Diagram
VPW SYMBOL
ENCODER /
DECODER
AND
ARBITRATION
SPI
SYSTEM
WATCHDOG AND
SLOW CLOCK DETECT
176 x 8
STATIC RAM
OSCILLATOR
AND
2
TIMER SYSTEM
PORT D
DIR
REG
PORT D
SFR
REG
PORT
A
REG
DATA
DIR
REG
PORT D
REG
INTERNAL
PROCESSOR
CLOCK
INTERNAL PROCESSOR CLOCK
SYMBOL INT
OSCB
38
39
RESET
IRQ
VPWOUT
VPWIN
SCK
MOSI
MISO
SS
37
36
32
26
25
33
50
23
24
34
35
49
48
47
46
45
44
43
42
19
18
17
16
15
TCAP
TCAP
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PD0
PD1
PD2, V2
PD3, V3
PD4, VR
P
P
V
SS
V
DD
22
7
TCMP
OSCIN OSCOUT
+
-
+
-
ADDRESS DRIVE
BUS DRIVE
BUS
CONTROL
13
12
9
6
5
14
5
5
5
5
5
5
5
5
D
D
D
D
D
D
D
D
4
4
4
4
4
4
4
4
A
A
A
A
A
A
A
A
4
4
4
4
4
A
A
A
A
A
DS
WE
CE
FS
RD
ALC
CPU
CONTROL
CPU
ALU
INDEX
REGISTER
CONDITION CODE
REGISTER
STACK
POINTER
PROGRAM
COUNTER HIGH
PROGRAM
COUNTER LOW
ACCUMULATOR
8
8
5
6
5
8
A
X
CC
S
PCH
PCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2P | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP9010 | Engine Knock Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7030A0M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2P | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030PD WAF | 制造商:Harris Corporation 功能描述: |
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