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參數(shù)資料
| 型號(hào)： | HIP7020AP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDIP8 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | HIP7020AP |
6
Waveshaper Circuit
This stage defines the transitions of high and low signal lev-
els to provide a uniform rise and fall time. The input signal to
the Waveshaper is the TX Buffer output and is an active high
signal. In the Waveshaper the Transmit signal is amplified
and compared to an internal reference voltage. The Wave-
shaper also provides waveform corner shaping on both the
positive and negative going transitions. The rise and fall time
of the serial waveform is set by the Waveshaper circuit and
an external programming resistor, R
S
that sets an internal
current reference at the R/F pin for control of the rise and fall
slopes of the waveform. As previously noted, to prevent
ground currents of the bus and node from affecting the
rise/fall time control of the Wave Shaper, the resistor, R
S
,
should be located as close as possible to the IC. To minimize
noise coupling to the R/F pin, the ground connection of R
S
should be made directly to the GND pin of the IC with no
other current flowing in the connecting line.
Wave Shaped Voltage Reference Drive, V
REF
The Wave Shaped Voltage Reference circuit sets a scaled
analog signal level and maintains a constant peak-to-peak
voltage during worst case battery voltage conditions, including
cold cranking. The analog signal from the Wave Shaped Volt-
age Reference circuit drives the Voltage-to-Current Converter
and a Level Shifter Interface to the bus driver transistor, Q1.
The Voltage-to-Current Converter, in addition to the waveform
leveling, helps to preserve low RFI and drive integrity. The
edges of the wave shaped waveform, V
REF
have well defined
rise and fall times and the knees of the waveform are smooth
and rounded as signal conditioning to reduce RFI.
Voltage-to-Current Converter
The Voltage-to-Current Converter determines the maximum
current to be sourced out to the J1850 bus and is designed
to source current proportional to the input signal from the
Wave Shaped Voltage Reference, V
REF
. The output of the
Voltage-to-Current Converter maintains drive integrity of the
V
REF
waveform without the use of feedback.
A small quiescent current source is supplied to maintain a
fixed minimum for each bus node. This precisely fixes the
quiescent current at low input signal drive to the Voltage-to-
Current Converter.
Voltage Controlled Current Driver, Q1
The Voltage Controlled Current Driver, Q1, controls the amount
of current sourced out to the J1850 Bus. The Wave Shaped
Voltage Reference, V
REF
, drives the base of Q1 and the Volt-
age-to-Current Converter drives the collector of Q1. Both volt-
age and current determine the drive level which is supplied to
the bus. When the Bus voltage is below the level determined by
the Voltage Reference, V
REF
, the Voltage Controlled Current
Driver allows more current to be sourced out to the J1850 Bus.
Voltage drive may increase as needed until the Bus voltage and
the Voltage Reference match or until the maximum current limit
is reached, as set by the Voltage-to-Current Converter. When
the Bus voltage is above the Voltage Reference the Voltage
Controlled Current Drive to the J1850 Bus is decreased.
Decreasing correction occurs until the Bus voltage and the Volt-
age Reference match or until zero current is being sourced.
Filter, Bus Receiver and Voltage Comparator
The Filter limits the high frequency bandwidth by external
resistor, R
F
, and the input capacitance of the Filter Block.
The on-chip Filter network and the external resistor, R
F
,
form a low pass filter to reject high frequency noise that may
be present on the bus. Resistor, R
F
, also provides isolation
protection from transients. The analog bus signal is passed
to the Bus Receiver and Voltage Comparator which deter-
mine when the bus is high or low as referenced to half the
nominal bus voltage at the BUS IN pin.
RX BUF (Receiver Output Buffer Interface)
The RX BUF function is a buffer for the logic output as
determined by the Bus Receiver and Voltage Comparator.
An open collector transistor supplies current switched output
to an external load resistor, R
D
. BUS IN data is converted to
serial CMOS/TTL logic data which is output at the RX pin of
the HIP7020. Resistor, R
D
, is biased from the digital 5V sup-
ply for optimum output drive levels to the logic circuits and to
avoid power-up of the digital parts via the transceiver.
Thermal Shutdown
Over-temperature shutdown with hysteresis is incorporated to
protect the IC under system failure conditions. Temperature
is sensed at the transistor, Q1. Thermal shutdown will occur
when the temperature of the chip reaches 150
o
C (minimum)
and will latch-off the HIP7020 Transmitter operation. A reset
occurs on the first positive edge transition of the next trans-
mit data bit after ~10
o
C decrease in chip temperature. Hys-
teresis in the thermal shutdown threshold is necessary to
allow the temperature to decrease to a safe operating tem-
perature, typically less than 140
o
C.
Diagnostic Loop-Back Mode Switch
The HIP7020 has an active low Loop-Back Enabled Mode
Switch which controls an internal signal path to provide diag-
nostic information. When Enabled, the Transmit/Receive sig-
nals are internally “Looped-Back” independent of the signal
conditions on the J1850 Bus. A return path validation indi-
cates proper action of the Bus Transceiver apart from the
J1850 Bus. In the Loop-Back Mode, the transistor, Q1 output
is forced low, preventing the output from sourcing current to
the bus. Loop-Back is not affected by thermal shutdown.
NOTE: The Block Diagram switch position is shown for Loop-Back op-
eration.Apull-downattheLB EN inputforcesanactivelowLoop-Back
mode as the default position when no connection is applied.
Operational Description
Bus Output Signal
The BUS OUT output drive from the HIP7020 conforms to
the SAE Standard
J1850 Class B Data Communication
Network Interface
document specifications. It meets these
requirements without oscillation, glitches or overshoots. The
digital signal to be transmitted is wave shaped and amplitude
controlled to produce an analog serial data waveform with
precisely defined rise and fall edges. Operational capability
covers a wide range of bus load resistances, capacitances
and characteristic impedance while complying with the arbi-
tration requirements of the Bus. Transient noise interference
HIP7020
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2 | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2M | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A2P | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7030A0 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A0M | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller Emulator Version |
| HIP7030A2 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2M | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
| HIP7030A2P | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:J1850 8-Bit 68HC05 Microcontroller |
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