參數(shù)資料
型號： HIP7010P
廠商： HARRIS SEMICONDUCTOR
元件分類： 網(wǎng)絡接口
英文描述： FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： DATACOM, INTERFACE CIRCUIT, PDIP14
文件頁數(shù)： 3/20頁
文件大?。?/td> 106K
代理商： HIP7010P
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V
DD
). . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with V
DD
Diode. . . . . . . . . . . . . . . . . . . .-0.3V to V
DD
+0.3V
Pins without V
DD
Diode . . . . . . . . . . . . . . . . . . . .-0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates
Thermal Resistance
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100
o
C/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120
o
C/W
Maximum Package Power Dissipation at +125
o
C
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW
Operating Temperature Range (T
A
) . . . . . . . . . . . -40
o
C to +125
o
C
Storage Temperature Range (T
STG
). . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150
o
C
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . .+265
o
C
θ
JA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . .-40
o
C to +125
o
C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . .(0.8V
DD
) to V
DD
Input Rise and Fall Time
CMOS Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
Electrical Specifications
T
A
= -40
o
C to +125
o
C, V
DD
= 5V
DC
±
10%, Unless Otherwise Specified
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current
Operating Current
I
OP
I
PD
I
STOP
CLK = 2.0 MHz
-
1.0
5.0
mA
Power-Down Mode (Note 1)
PD = 1
-
50
150
μ
A
Clock Stopped (Note 2)
CLK = V
SS
or V
DD
-
5.0
50
μ
A
Input High Voltage
CMOS Level (SIN, STAT, RDY, TEST)
V
IH
0.7V
DD
0.8V
DD
-
V
DD
V
DD
V
Schmitt Trigger (RESET, CLK, VPWIN)
-
V
Input Low Voltage
CMOS Level (SIN, STAT, RDY, TEST)
V
IL
V
SS
V
SS
-
0.3V
DD
0.2V
DD
V
Schmitt Trigger (RESET, CLK, VPWIN)
-
V
High Level Input Current
(CLK, VPWIN, RESET)
I
IH
V
IN
= V
DD
-1
0.001
1
μ
A
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
100
200
500
μ
A
Low Level Input Current
(CLK, VPWIN, RESET)
I
IL
V
IN
= V
SS
-1
-0.001
1
μ
A
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
-10
-0.01
10
μ
A
Output High Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
V
OH
I
LOAD
= 0.8 mA
V
DD
-0.8
-
-
V
Output Low Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
V
OL
I
LOAD
= -1.6 mA
-
-
0.4
V
High Impedance Leakage Current
Three-State with Pull-Down (SCK, SOUT)
I
OZ
V
OUT
= V
DD
V
OUT
= V
SS
100
200
500
μ
A
-10
10
μ
A
Schmitt Trigger Hysteresis Voltage
(RESET, CLK, VPWIN)
V
HYS
0.2
0.5
2.0
V
NOTES:
1. SIN, STAT, RDY, and TEST = V
SS
;
SACTIVE, SCK, and SOUT unconnected;
VPWIN = V
DD
; CLK = 10MHz.
2. SIN, STAT, RDY, and TEST = V
SS
;
SACTIVE, SCK, and SOUT unconnected; VPWIN = V
DD
; PD = 1.
HIP7010
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相關代理商/技術參數(shù)
參數(shù)描述
HIP7010P WAF 制造商:Harris Corporation 功能描述:
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HIP7020AB 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems
HIP7020AP 制造商:Harris Corporation 功能描述:
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