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參數(shù)資料
| 型號： | HIP7010P |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDIP14 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 106K |
| 代理商： | HIP7010P |
15
tures to create a complete J1850 VPW node. See the
Applications Information
section for typical algorithms.
The State Machine Logic (STATE)
The State Machine Logic (STATE) of the HIP7010, is a
sequential state machine implementation of the J1850 VPW
data link layer. STATE controls data flows within the HIP7010
and between the Host and the J1850 bus.
When receiving messages, STATE monitors the input from
the SENDEC, building byte sized chunks to send to the Host.
As each byte is assembled, STATE transfers the result to the
Host via the Serial interface, as an unsolicited transfer. Upon
receipt of a complete message (recognized by EOD), STATE
verifies both the CRC and bit counts and sets appropriate
Status Register flags.
When transmitting messages from the Host to the J1850
bus, STATE waits for the first RDY input transition, after
which it retrieves the first byte from the Host and initiates the
message with an SOF. Each bit of the Host’s message byte
is transferred to the J1850 bus via the SENDEC. When the
transfer of a byte is complete, STATE checks for a new RDY
(if there is one), retrieves the associated byte, and again
transfers the byte via the SENDEC to the J1850 bus. After
retrieving each byte from the Host, STATE checks to see if
the long RDY format was used, which indicates this is the
end of the Host’s message. If the message is complete,
STATE transfers the final byte to the J1850 Bus and then,
automatically, sends the computed CRC to the J1850 bus.
Throughout the transmission of a message from the Host to
the J1850 bus, STATE monitors the symbols reflected back
via the SENDEC and handles all bus conditions such as loss
of arbitration, illegal bits, Break, bad CRC, and missing bits.
STATE also catches Host errors including failure to set the
RDY line in time for the next byte transfer, attempting to ini-
tiate a new message more than 96
μ
s after IDLE has gone
away, and inappropriate use of the STAT line (i.e., requesting
a Status/Control Register transfer during an unsolicited
transfer of the reflected data).
In 4X mode VPWOUT is disabled in hardware, but STATE
will attempt to transmit if RDY is strobed. This results in
STATE clearing IDLE and waiting for the leading edge of
SOF. Since VPWOUT is blocked STATE will only recover if
another node’s SOF is received or NXT is set. It is the Host’s
responsibility to refrain from transmitting in 4X mode.
The Control Register bits influence STATE. If ACK is set,
STATE handles sequencing of the requested IFR. The flow
consists of waiting for an EOD, sending the appropriate Nor-
malization Bit (Type 1/2 vs Type 3 IFR), transferring the IFR
byte(s) from the Host to the J1850 bus, handling arbitration,
and finally adding the CRC to Type 3 IFRs. As with normal
transmissions, STATE contains error handling to react appro-
priately to all J1850 bus conditions.
Detection of an Idle on the bus causes STATE to set the IDLE
pin. STATE clears the IDLE pin upon receipt of a transition on
the VPWIN line or when the Host initiates a new message.
Detection of a Break on the J1850 bus causes an interrupt
input to STATE which causes the HIP7010 to cease any cur-
rent transmission and enter a wait for IDLEmode.
Effects of Resets and Power-Down
Resets
A Power-On reset, a Slow Clock Detect reset, and a low on
the RESET pin all have an identical effect on the operation of
the HIP7010. All resets are asynchronous and immediately
do the following:
VPWOUT is forced low.
The HIP7010 is set to RESTART mode
The internal divide-by is set to sixteen and held at that
value until the RESTART mode ends.
SACTIVE is forced high and SCK and SOUT are set to a
high impedance state.
The ACK, MACK, NXT, PD, and 4X bits are cleared in the
Control Register.
All Status Register bits are cleared (except bit 4, FTU,
which is set to a 1).
IDLE is forced high and held high for 17 CLKs after the
source of the reset is removed. After 17 CLKs, IDLE is
forced low. IDLE Remains low until 40 CLKs +1.5
μ
s after
the first Status/Control Register transfer.
The SENDEC is reset, holding the symbol timer at a count
of 0 and clearing the 3-bit VPWIN filter to all 0’s, until the
RESTART mode ends.
STATE is held in a reset loopuntil the RESTART mode
ends. While STATE is in the reset loop, transitions on the
RDY pin are ignored.
The RESTART mode is entered by any reset and ends when
the first Status/Control Register transfer has been com-
pleted. Upon exiting the RESTART mode the HIP7010
enters its normal RUN mode This is reflected in the clearing
of the FTU bit of the Status Register.
When the RESTART mode ends and the RUN mode begins,
the internal divide-by is set to the value programmed via
DS2-DS0 in the Control Register. The IDLE pin is driven
high after 40 CLKs, the SENDECs counter and VPWIN filter
begin operating, and STATE begins monitoring the outputs
of SENDEC looking for an Idle.
The HIP7010 remains in RUN mode until another reset
occurs or the POWER-DOWN mode is entered.
Power-Down
The POWER-DOWN mode of the HIP7010 is entered by set-
ting the PD bit in the Control Register (see
Control Register
for more information). Setting the PD bit can only be done
when the HIP7010 is driving the IDLE pin low. Once set, the
PD forces the HIP7010 to the POWER-DOWN mode 2
μ
s
after the completion of the Status/Control Register transfer.
While in the POWER-DOWN mode the CLK input is internally
gated off, minimizing power dissipation. The Slow Clock
Detect is inhibited while in the POWER-DOWN mode.
A return to the RUN mode from the POWER-DOWN mode is
normally caused by a low level on VPWIN. During POWER-
HIP7010
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相關(guān)代理商/技術(shù)參數(shù) |
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| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
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| HIP7020AP | 制造商:Harris Corporation 功能描述: |
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