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參數(shù)資料
| 型號(hào)： | HIP7010B |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | J1850 Byte Level Interface Circuit |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO14 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 106K |
| 代理商： | HIP7010B |
17
Error Handling
The Status Register
The various flags in the Status Register can be used to
detect many errors which would typically be generated by
system noise, errant nodes, or improperly designed Host
code. It is good practice to maintain error counts in the Host
for service reporting and to trigger recovery procedures.
Whenever the ERR or CRC are set in the Status Register,
the current message is aborted and the BLIC enters a “wait
for Idle” mode. Following is a detailed listing of the errors
which can be trapped by reading the Status Register.
Errors Which Set the ERR Flag
The ERR flag will be set whenever:
1.
A noise pulse (i.e., a symbol less than TV1
MIN
) is received
- including while waiting for an Idle.
An illegal symbol, (i.e., a symbol other than a TV1, TV2, or
Break) is received in the middle of a message which is
being received or transmitted.
A message with an incomplete byte is received (i.e., total
data bit count not equal to 0 modulo 8).
The Host attempts to initiate a message more than
TV2
MIN
(96
μ
s) after the IDLE line goes high.
An improperly framed message is received (i.e., SOF not
equal to TV3, wrong EOD, EOF, or NB widths).
An SOF occurs less than TV4 after the end of a Type 0
message.
While transmitting a message that the Host fails to assert
RDY prior to a data transfer.
The Host fails to use the long form of RDY to indicate the
last byte of a message.
The Host attempts to transmit an IFR by setting ACK but
fails to assert RDY prior to 135
μ
s after the CRC.
10. The Host attempts to transmit a single byte (Type 1 or
Type 2) IFR by setting ACK but without using the long
form of RDY for the
first
byte transfer.
11. The Host asserts STAT during a data byte transfer.
12. While transmitting, a Status/Control Register transfer is in
progress
when a data byte transfer begins.
13. A transition has occurred on the VPWOUT pin and the
reflected transition has not been detected on VPWIN
(echo fail).
14. A failure occurs during TEST mode.
15. A
low pulse <7
μ
s
occurs on VPWIN during the POWER-
DOWN mode.
2.
3.
4.
5.
6.
7.
8.
9.
Errors Which Don’tSet the ERR Flag
Due to various considerations, some errors which the user
might otherwise expect to be trapped by ERR are not. These
include:
1.
A zero length message (SOF followed by EOD) will not set
ERR, but will set the CRC flag.
Any symbol, other than a noise pulse, is ignored while
2.
waiting for an Idle. That is to say that the current message
is discarded. “Waiting for Idle” happens following: Reset,
setting of NXT, any error which sets ERR (except asserting
STAT during a data transfer), a CRC error, a Break, or fol-
lowing EOD after a Type 1, 2, or 3 message.
After a
Type 1, 2, or 3 message, a second NB or an SOF
for a new message received before EOF will be ignored.
Any following symbols will be ignored until EOF is
detected. This implies that if two messages appear on the
bus with less than an EOF between them the second mes-
sage will be ignored, but no error generated. Similarly, if an
IFR is attached to a message after EOD and a second NB
is generated an EOD after the initial IFR, the NB and all
succeeding symbols will be ignored until Idle is detected.
No error will be generated.
3.
Errors Which Set the CRC Flag
The CRC flag will be set whenever:
1.
The CRC check byte of the body of any type message is
bad (any IFR will be aborted/ignored).
All components of a Type 3 message frame are good
except the IFR’s CRC check byte.
A zero length message (SOF followed by EOD) is received.
2.
3.
Host Time-outs
Other classes of errors, including catastrophic failure of the
J1850 bus, can sometimes only be detected by monitoring
the time between successfully received messages and/or
the delay between IDLEs - when the time exceeds some limit
the Host assumes that a bus fault exists and attempt to iso-
late the cause (perhaps using the TEST pin) and perform
recovery/”limp home” actions.
Error Recovery
If errors are detected on multiple occasions or a Host time-
out occurs, the BLIC should be reset by lowering RESET or
stopping the CLK (or setting NXT if the RESET or CLK pin is
not controllable), and DS2-0 should be re-initialized in the
Control Register.
If resetting the BLIC doesn’t eliminate the error condition, a
test procedure should be entered using TEST and loopback
modes.
HIP7010
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PDF描述 |
|---|---|
| HIP7010P | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020 | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7010P | 制造商:Rochester Electronics LLC 功能描述:J1850 JBLIC (DIP) - Bulk |
| HIP7010P WAF | 制造商:Harris Corporation 功能描述: |
| HIP7020 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
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