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參數(shù)資料
| 型號： | HIP7010B |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | J1850 Byte Level Interface Circuit |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO14 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 106K |
| 代理商： | HIP7010B |
16
DOWN the input signal is not filtered via the
7
μ
s
digital filter (no
clocks are available to drive the digital filter). Without filtering in
place it is possible for a noise spike, less than
7
μ
s
wide, to
wake-upthe HIP7010. In such a case the HIP7010 returns to
RUN mode, but the spike is rejected by the now running, digital
filter and the bus continues in the Idle state. To notify the Host
when such spurious wake-ups occur, STATE monitors the out-
put of the digital filter and if, within 12
μ
s after the wake-up, the
digital filter doesn’t indicate VPWIN is low, STATE pulses IDLE
high for 2
μ
s and then drives it low again. The HIP7010 is now in
the RUN mode. It is the responsibility of the Host to recognize
the pulse on the IDLE pin and set PD in the Control Register to
reenter the POWER-DOWN mode. In systems where the Host
directly monitors the VPWIN pin during POWER-DOWN, moni-
toring the IDLE pin may not be necessary.
One of the mechanisms to exit POWER-DOWN is to provide a
high level on the RDY pin. Since this is a level sensitive event
the HOST must ensure that RDY is not already high when the
PD bit is set in the Control Register. A well behaved Host will
control this properly. However, in the event RDY is high when
PD is set, a 12
μ
s time-out will occur similar to that described
for waking-up with a noise pulse on VPWIN. After the time-
out, IDLE will pulse high for 2
μ
s then low again. The Host
should react to this pulse appropriately.
Test Mode
Overview
When the TEST Pin of the HIP7010 is driven high, it modi-
fies the operation of the BLIC in two ways:
1.
It inhibits receipt of bus signals on the VPWIN pin and
internally routes the VPWOUT signal to the VPWIN
input. During this “l(fā)oopback” mode of operation the
VPWOUT pin will continue to operate
The State Machine which controls the operation of the
HIP7010 is extended to include a special TEST Sequence.
The TEST Sequence can only be entered from one loca-
tion in the normal State Machine flow. This point can con-
veniently be reached following reset of the BLIC or by
setting the NXT bit in the BLIC’s Control Register.
2.
Entering the TEST Sequence
Entry into the TEST Sequence of the BLIC’s State Machine
requires that the TEST pin is high
and
the State Machine is
at it’s “start”. The State Machine will always pass through
its
starting point at certain identifiable times:
1.
2.
3.
Following the first Status/Control Transfer after a Reset
Following completion of a J1850 message (i.e., after EOD)
Following abortion of a message frame due to noise, bad
symbol, bad CRC, receipt of a Break, etc.
Following setting of the NXT bit in the Control Register
As are all states, the starting point is a transitory state. Once
entered, the State Machine will remain at its start only until
the bus has been low for a TV4 min (i.e., EOF, 239
μ
s). To
ensure proper synchronization, the TEST Sequence should
generally be entered only after a Reset or after setting the
NXT bit in the BLIC’s Control Register.
4.
Test Block 1
Once the TEST Sequence has been entered, IDLE will go
low. Once IDLE has gone low, each time that RDY is pulsed
(with the
short
form of RDY) it will result in an exchange of
data between the Host’s SPI register and the BLIC’s data
register. Following a reset, the BLIC’s data register will con-
tain $00. For all other exchanges during the TEST sequence
the BLIC will give back to the Host the byte it supplied during
the prior exchange. During each exchange the IDLE pin will
go high and return low when the exchange is complete. Fol-
lowing each exchange the Host should query the BLIC’s Sta-
tus Register by pulsing STAT. All flags should be clear.
This section of the TEST Sequence not only checks proper
operation of the Serial Register of the BLIC, the TEST, IDLE,
RDY, and STAT pins but it also does an internal verification of
>70% of the inputs of the BLIC’s State Machine.
Test Block 2
The TEST Sequence can now be exited by lowering TEST
and setting the NXT bit in the Control Register, or the second
portion of the TEST Sequence can be invoked by leaving
TEST high and doing one last transfer of an $FF using the
long
form of RDY. Following this exchange the BLIC will send
a high TV2 followed by a low TV1 followed by a high noise
pulse (to prevent bus interference the HIP7020 Transceiver
should be in Loopback Mode during this sequence). Following
the noise pulse, the State Machine will return to the start of
the TEST Sequence and IDLE will go low. If all tests were suc-
cessful the ERR bit should be set in the Status Register (due
to the noise pulse) and the Serial Data Register should have
been set to $00 (done following the TV1). This can be verified
by doing a STAT transfer followed by a RDY transfer. Normally
the TEST Sequence would now be exited by lowering TEST
and setting NXT in the Control Register.
The second block of the TEST Sequence boosts the number
of tested State Machine inputs to over 90%.
Using TEST for Loopback Operation
Whenever TEST is high the BLIC is operating in “l(fā)oopback”
mode. This provides a convenient means to isolate faults
between the Bus, the Transceiver, and the BLIC. It also sim-
plifies extended testing of the BLIC’s Symbol Genera-
tion/Detection,
Message
Generation/Detection logic.
Handling
and
CRC
To isolate Module faults from Bus faults: place the HIP7020
Transceiver in loopback (by lowering LBE) and send a mes-
sage. Verify the message and CRC are properly reflected
and the Status bits are clear. If all are good, the fault can be
assumed to be on the output of the Transceiver or on the bus
itself. If all are not good, leave the Transceiver in loopback
and place the BLIC in loopback (to place the BLIC in loop-
back, wait for IDLE to go low and then raise TEST) and send
a message again verifying that the message and CRC are
properly reflected and that the Status bits are clear. If all are
good the Transceiver or VPWOUT or VPWIN of the BLIC are
faulty. If all are not good the fault is either internal to the BLIC
or is a problem with the Host/BLIC interface. If the TEST
Sequence can be properly run the problem has been iso-
lated to an internal fault of the HIP7010.
HIP7010
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7010P | 制造商:Rochester Electronics LLC 功能描述:J1850 JBLIC (DIP) - Bulk |
| HIP7010P WAF | 制造商:Harris Corporation 功能描述: |
| HIP7020 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
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