參數(shù)資料
型號： HIP6501ACBZ
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Triple Linear Power Controller with ACPI Control Interface
中文描述： 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝： ROHS COMPLIANT, PLASTIC, MS-012-AC, SOIC-16
文件頁數(shù)： 7/14頁
文件大小： 340K
代理商： HIP6501ACBZ
7
FN4749.6
December 30, 2004
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5V
DUAL
plane supports sleep states.
As seen in Table 3, 2.5/3.3V
MEM
output is maintained in S3
(Suspend-To-RAM), but not in S4/S5 state. The dual-voltage
support accommodates both SDRAM as well as RDRAM
type memories.
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S4/S5) and vice versa.
Functional Timing Diagrams
Figures 4-8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
Not shown in these diagrams is the de-glitching feature used
to protect against false sleep state tripping. Once the status
of the S3 pin changes, an internal timer is activated. If at the
end of the timeout period (typically 200
μ
s) the input pins
present a valid state change request, then the controller
transitions to the new configuration. Otherwise, the
previously attained valid state is maintained until valid
control signals are received from the system. This particular
feature is useful in noisy computer environments if the
control signals have to travel over significant distances.
TABLE 2. 5V
DUAL
OUTPUT (V
OUT3
) TRUTH TABLE
EN5VDL
S5
S3
5VDL
COMMENTS
0
1
1
5V
S0, S1 STATES (Active)
0
1
0
0V
S3
0
0
1
Note 5 Maintains Previous State
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 STATES (Active)
1
1
0
5V
S3
1
0
1
Note 5 Maintains Previous State
1
0
0
5V
S4/S5
NOTE:
5. Combination not allowed.
TABLE 3. 2.5/3.3V
MEM
OUTPUT (V
OUT2
) TRUTH TABLE
R
SEL
S5
S3
2.5/3.3V
MEM
COMMENTS
1k
1
1
2.5V
S0, S1 STATES (Active)
1k
1
0
2.5V
S3
1k
0
1
Note 6
Maintains Previous State
1k
0
0
0V
S4/S5
10k
1
1
3.3V
S0, S1 STATES (Active)
10k
1
0
3.3V
S3
10k
0
1
Note 6
Maintains Previous State
10k
0
0
0V
S4/S5
NOTE:
6. Combination not allowed.
FIGURE 4. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 1
FIGURE 5. 3V
DUAL
AND 5V
DUAL
TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 0
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
5VSB
12V
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
HIP6501A
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