參數(shù)資料
型號(hào): HIP6018B
廠商: Intersil Corporation
英文描述: 100,000 System Gate FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 先進(jìn)的雙PWM和線性功率控制
文件頁(yè)數(shù): 8/14頁(yè)
文件大小: 134K
代理商: HIP6018B
2-245
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
OUT1
to increase. When the output exceeds the
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on as required in order to regulate V
OUT1
to 1.15 x
DACOUT. This blows the input fuse and reduces V
OUT1
.
The fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
OUT1
is
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V
OUT1
to 1.26V.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
DS(ON)
to monitor the current for protection
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB2 and FB3 for under-voltage to protect
against excessive currents.
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the output inductor (L
OUT1
). At time
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (I
D
r
DS(ON)
) exceeds the level programmed by
R
OCSET
. This inhibits all outputs, discharges the soft-start
capacitor (C
SS
) with a 11
μ
A current sink, and increments the
counter.C
SS
recharges at T2 and initiates a soft-start cycle
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT pin.
The linear regulator operates in the same way as PWM1 to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause FB2 or FB3 to fall
below the linear under-voltage threshold, the LUV signal
sets the over-current latch if C
SS
isfully charged. Blanking the
LUV signal during the C
SS
charge interval allows the linear
outputs to build above the under-voltage threshold during
normal start-up. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistor R
OCSET1
programs the over-current trip level for the
PWM converter. As shown in Figure 9, the internal 200
μ
A
current sink develops a voltage across R
OCSET
(V
SET
) that is
referenced to V
IN
. The DRIVE signal enables the over-current
comparator (OVER-CURRENT1). When the voltage across the
upper MOSFET (V
DS(ON)
) exceeds V
SET
, the over-current
comparator trips to set the over-current latch. Both V
SET
and
V
DS
are referenced to V
IN
and a small capacitor across
R
OCSET
helps V
OCSET
track the variations of V
IN
due to
MOSFET switching. The over-current function will trip at a peak
inductor current (I
PEAK)
determined by:
FAULT
LATCH
S
R
Q
POR
COUNTER
OC1
OV
LUV
+
-
+
-
0.15V
4V
SS
VCC
FAULT
R
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
UP
OVER
CURRENT
LATCH
INHIBIT
S
R
Q
S
0A
0V
2V
4V
FIGURE 8. OVER-CURRENT OPERATION
TIME
T1
T2
T3
T0
T4
F
0V
10V
OVERLOAD
APPLIED
C= 1
C= 2
C= 3
FAULT
REPORTED
IPEAK=
)
IOCrDS ON
HIP6018B
相關(guān)PDF資料
PDF描述
HIP6018BCB FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP6019 FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP6019CB Advanced Dual PWM and Dual Linear Power Control
HIP6019EVAL1 Advanced Dual PWM and Dual Linear Power Control
HIP6019 5-BIT PROGRAMMABLE SYNCHRONOUS BUCK, NON-SYNCHRONOUS,ADJUSTABLE LDO AND 200mA ON-BOARD LDO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP6018B_05 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced PWM and Dual Linear Power Control
HIP6018BCB 功能描述:IC REG TRPL BCK/LINEAR 24-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 + 切換式 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 拓?fù)?降壓(降壓)同步(3),線性(LDO)(2) 功能:任何功能 輸出數(shù):5 頻率 - 開(kāi)關(guān):300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅(qū)動(dòng)器:無(wú) 帶監(jiān)控器:無(wú) 帶序列發(fā)生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
HIP6018BCB-T 功能描述:IC REG TRPL BCK/LINEAR 24-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 + 切換式 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 拓?fù)?降壓(降壓)同步(3),線性(LDO)(2) 功能:任何功能 輸出數(shù):5 頻率 - 開(kāi)關(guān):300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅(qū)動(dòng)器:無(wú) 帶監(jiān)控器:無(wú) 帶序列發(fā)生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
HIP6018BCBZ 功能描述:電壓模式 PWM 控制器 ADV DL PWM "3 IN1" W/LWER DAC RNG RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開(kāi)關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel
HIP6018BCBZ-T 功能描述:電壓模式 PWM 控制器 ADV DL PWM "3 IN1" W/LWER DAC RNG RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開(kāi)關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel