參數資料
型號: HIP6004B
廠商: Intersil Corporation
英文描述: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor(脈沖帶寬調節(jié)控制和輸出電壓檢測電路)
中文描述: 巴克和同步整流(PWM)控制器和輸出電壓監(jiān)視器(脈沖帶寬調節(jié)控制和輸出電壓檢測電路)
文件頁數: 9/12頁
文件大?。?/td> 160K
代理商: HIP6004B
2-82
Compensation Break Frequency Equations
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are a function of the switching frequency and the ripple
current. The load transient requirements are a function of
the slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a mix
of capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1
μ
F
ceramic capacitors in the 1206 surface-mount package.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines
the converter’s ripple current and the ripple voltage is a
function of the ripple current. The ripple voltage and current
are approximated by the following equations:
Increasing the value of inductance reduces the ripple
current and voltage. However, the large inductance values
reduce the converter’s response time to a load transient.
F
Z1
2
1
------------------------------------
=
F
Z2
1
R
3
)
x C
3
--------------------------+
=
F
P1
2
π
x R
2
x
2
1
C
2
+
---------------------
--------------------------------------------------------
=
F
P2
3
3
------------------------------------
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
2
/R
1
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
I =
V
IN
- V
OUT
Fs x L
V
OUT
V
IN
V
OUT
=
I x ESR
x
HIP6004B
相關PDF資料
PDF描述
HIP6004 Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor(脈沖帶寬調節(jié)控制和輸出電壓檢測電路)
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相關代理商/技術參數
參數描述
HIP6004B_03 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
HIP6004BCB 功能描述:IC CTRLR PWM VOLTAGE MON 20-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源,ICERA E400,E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA,WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR)
HIP6004BCB-T 功能描述:IC CTRLR PWM VOLTAGE MON 20-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源,ICERA E400,E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA,WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR)
HIP6004BCBZ 功能描述:電壓模式 PWM 控制器 PWM CNTRLR 3 5 TO 1 3 DAC RNG 20LD RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel
HIP6004BCBZA 功能描述:電壓模式 PWM 控制器 W/ANNEAL PWM CNTRLR 3 5 TO 1 3 DAC RNG RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel