7
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the HIP6003 within 3 inches of the MOSFET, Q1.
The circuit traces for the MOSFETs gate and source
connections from the HIP6003 must be sized to handle up to
1A peak current.
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a buck
converter. The output voltage (V
OUT
) is regulated to the
Reference voltage level. The error amplifier (Error Amp)
output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC.
L
O
CO
UGATE
PHASE
Q1
D2
V
IN
V
OUT
RETURN
HIP6003
C
IN
L
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
+12V
HIP6003
SS
GND
V
CC
BOOT
D1
L
O
CO
V
OUT
L
Q1
D2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
V
OUT
OSC
REFERENCE
LO
CO
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6003
Z
IN
COMPARATOR
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
FIGURE 8. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
HIP6003