參數資料
型號: HIP5062DW
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 10 A DUAL SWITCHING CONTROLLER, 1100 kHz SWITCHING FREQ-MAX, UUC40
封裝: WAFER
文件頁數: 4/7頁
文件大?。?/td> 655K
代理商: HIP5062DW
4
V
TH
IFRO
Voltage at IRFO that disables
PWM. This is due to low load
current
116
-
250
mV
I
TH
IFRO
Voltage at IRFO to enable SHRT
output current. This is due to
Regulator Over Current Condi-
tions
6.85
-
7.65
V
I
SHRT
SHRT Output Current, During
Over-Current
V
IRFO
= 7.7V
-75
-
-33
μ
A
V
TH
SHRT
Threshold voltage on SHRT to
set FLTN latch
V
DDD
= 11V
-
5
-
V
I
GAIN
I
PEAK
(DMOS
DRAIN
)/I
IRFI
I (DMOS
DRAIN
)/
t = 1A/ms
2.0
-
3.2
A/mA
R
IRFI
IRFI Resistance to GND
I
IRFI
= 2mA
150
-
360
t
RS
Current Comparator Response
Time (Note 1)
I (DMOS
DRAIN
)/
t > 1A/
μ
s
-
30
-
ns
MCPW
Minimum Controllable Pulse
Width (Note 1)
25
50
100
ns
MCPI
Minimum Controllable DMOS
Peak Current (Note 1)
125
250
500
mA
START-UP
V+
Rising V+ Power-On Reset
Voltage
23
-
26.3
V
Falling V+ Power-Off Set
Voltage
-
15
-
V
V+ Power-On Hysteresis
9.5
-
11.8
V
V
TH
PSEN
Voltage at PSEN to Enable
Supply
V
DDD
= 11V
3.6
-
6.5
V
r
PSEN
Internal Pull-Up Resistance, to
V
DDD
-
12
-
K
I
SFST
Soft-Start Charging Current
V
SFST
= 0V to 11V
-1.5
-1.0
-0.65
μ
A
I
PSOK
PSOK High-State Leakage
Current
SFST = 11V, PSOK = 12V
-1
-
1
μ
A
V
PSOK
PSOK Low-State Voltage
SFST = 0V, I
PSOK
= 1mA
-
-
0.4
V
V
TH
SFST
PSOK Threshold, Rising V
SFST
V
DDD
= 11V
8.1
-
9.9
V
THERMAL MONITOR
TEMP
Substrate Temperature for
Thermal Monitor to Trip (Note 1)
TMON = 0V
105
-
135
o
C
NOTE:
1. Determined by design, not a measured parameter.
Electrical Specifications
V+ = 36V, Channels 1 and 2, T
J
= 0
o
C to +110
o
C; Unless Otherwise Specified
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIP5062
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