參數資料
型號： HIP5062DW
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： 10 A DUAL SWITCHING CONTROLLER, 1100 kHz SWITCHING FREQ-MAX, UUC40
封裝： WAFER
文件頁數： 3/7頁
文件大?。?/td> 655K
代理商： HIP5062DW
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 42V
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A
DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V
Operating Junction Temperature Range . . . . . . . . . .0
o
C to +110
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . -55
o
C to +150
o
C
Thermal Resistance
(Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3
o
C/W Max
0.050” Thick Copper Heat Sink)
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110
o
C
(Controlled By Thermal Shutdown Circuit)
θ
JC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V+ = 36V, Channels 1 and 2, T
J
= 0
o
C to +110
o
C; Unless Otherwise Specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
I+
Supply Current
V+ = 42V, PSEN = 12V
-
24.7
30
mA
V
DDA
Internal Regulator Output
Voltage
V+ = 30V to 42V, I
OUT
= 0mA
11.7
-
13.3
V
V+ = 30V to 42V, I
OUT
= 30mA
11.5
-
13.3
V
SLRN = 12V, I
OUT
= 0mA
11.5
-
13.3
V
VINP
Reference Voltage
VDDA = SLRN = 12V, I
VINP
= 0mA
5.01
5.1
5.19
V
R
VINP
VINP Resistance
VINP = 0
-
900
-
ERROR AMPLIFIERS
| V
IO
|
Input Offset Voltage
(REG - VINP)
I
VCMP
= 0mA
-
-
10
mV
R
IN
VREG
Input Resistance to GND
VREG = 5.1V
39
-
85
k
g
m
(VREG)
VREG Transconductance
(I
VCMP
/(VREG - VINP)
VCMP = 1V to 8V, SFST = 11V
15
30
50
mS
g
m
(SFST)
SFST Transconductance
I
VCMP
/(VREG - SFST)
V
SFST
< 4.9V
0.8
-
6
mS
I
VCMP
Maximum Source Current
VREG = 4.95V, VCMP = 8V
-2.5
-
-0.75
mA
Maximum Sink Current
VREG = 5.25V, VCMP = 0.4V
0.75
-
2.5
mA
OVTH
Over-Voltage Threshold
Voltage at VREG for FLTN to be
latched
6.05
-
6.5
V
CLOCK
fq
Internal Clock Frequency
XCKS = 12V, V
DDD
= 12V
0.9
1.0
1.1
MHz
V
TH
CKIN
External Clock Input Threshold
Voltages
33
-
66
%V
DDD
DMOS TRANSISTORS
r
DS(on)
Drain-Source On-State
Resistance
I Drain = 2.5A, V
DDD
= 11V,
T
J
= +25
o
C
-
-
0.22
I
DSS
Drain-Source Leakage Current
Drain to Source Voltage = 60V
-
1
100
μ
A
CURRENT CONTROLED PWM
|V
IO
| VCMP
Buffer Offset Voltage (VCOMP -
V
IFRO
)
IFRO = 0mA to -5mA,
VTCN = 0.2V to 7.6V,
VCMP2 = 0.2V to 7.6V
-
-
125
mV
HIP5062
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