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參數(shù)資料
| 型號： | HIP5020 |
| 廠商： | Intersil Corporation |
| 英文描述： | High-efficiency, Buck Converter Controller(高效電源控制器) |
| 中文描述： | 高效率，降壓轉換器控制器（高效電源控制器） |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 128K |
| 代理商： | HIP5020 |
2-20
Design Information
The HIP5020 is optimized for battery power systems with a
4.5V to 18V input. The integrated MOSFETs along with an
LC output filter form a synchronous rectified, step-down
(buck) converter. The output is regulated at high output
current by peak-current-mode PWM control. At light loads,
the control automatically transitions to hysteretic mode to
regulate the output.
Detailed Operating Description
The following description refers to symbols and components
in the Functional Block Diagram and Figure 1. Figure 1
shows the HIP5020 in a DC/DC converter.
Operating Modes
The HIP5020 has 4 modes of operation; Shutdown, Start-up,
Run and Hysteretic modes. The controller draws only 2
μ
A
from the input supply in the Shutdown mode. This mode is
activated when the SD pin is high. The controller enters the
Start-up mode by releasing the SD pin, and the charge pump
turns-on to increase V
CC
above the under-voltage lockout
threshold. In the Start-up mode, the voltage on the SOFT pin
increases at a rate set by the capacitor on the SOFT pin. The
SOFT voltage limits the rate-of-rise of output voltage. The
output voltage is regulated with peak current control in the
Run mode at high output current. For low output currents, the
controller automatically transitions to Hysteretic mode for
output regulation. In this mode, the hysteretic comparator
cycles the control on (RUN = High) and off (RUN = Low) as a
function of the output voltage level. When off (RUN = Low),
bias power is removed from most of the control’s functions
(only the reference and hysteretic comparator operate with
RUN = Low). The converter replenishes the output capacitor
charge with short duration power cycles (RUN = High) and the
converter dissipates very little average power. A resistor (R4)
programs the load current boundary (HMI) between the Run
and Hysteretic modes.
Run Mode
The HIP5020 operates in Run mode at high output currents.
Each clock cycle of the oscillator sets the PWM Latch and
turns-on the high side MOSFET (See the Functional Block
Diagram). The current sensor supplies a voltage
proportional to the current in the high side MOSFET. The
PWM Comparator resets the PWM latch once the current
signal exceeds the summation of the error amplifier and
slope signals. The upper MOSFET turns off and the PWM
latch enables the lower gate drive and logic. The current in
the output inductor continues to flow, reducing the PHASE
voltage (by displacing charge on the capacitances of the
PHASE pin). The lower MOSFET turns-on after the voltage
on the PHASE pin falls to ground as monitored by the phase
comparator. The lower MOSFET remains ‘on’ for continuous
output inductor current until the next cycle. For discontinuous
inductor current operation, the phase comparator signals the
lower gate drive to turn-off the lower MOSFET when the
inductor current reaches zero by monitoring the phase
voltage (r
DS(ON)
* I).
The HIP5020 regulates the output voltage with peak-current
PWM control in Run mode. The peak-current-mode
feedback, the MOSFETs and output inductor, L1 are all parts
of the peak-current control loop. An outer voltage regulation
loop then programs the peak current to the level required.
When averaged over many switching cycles, the entire peak-
current control loop can be simplified and described as a
voltage controlled current source. Figure 5 shows a
simplified diagram of this operation. The current source
supplies the output capacitor and load. The outer voltage
regulation loop consists of an error amplifier and
compensation components. The error amplifier programs the
inductor current (as described above) to the value required
to regulate the output voltage. Both the error amplifier and
hysteretic comparator monitor the feedback (FB) pin. During
the Run mode, the feedback node voltage (V
FB
) is held to
the reference voltage (REF) by the voltage feedback loop.
V
FB
is related to V
o
, R1 and R2.
Limiting the error amplifier output voltage range provides
both current-limit protection and a mechanism for setting
the load current boundary between the Run and Hysteretic
modes. Figure 6 shows the modes of operation as a
function of the error amplifier output and load current. The
error amplifier output voltage tracks the inductor current.
The upper error amplifier clamp limits the peak inductor
current which reduces the pulse-width (or duty factor). This
reduces the output voltage with a constant current
characteristic. The lower error amplifier limit sets the
minimum inductor current. For load current demand below
the minimum inductor current, the excess current adds
charge to the output capacitor and the output voltage
increases. The voltage on the feedback (FB) pin also
ERROR
AMP
-
+
OUTPUT
CAPACITOR
LOAD
REF
+
-
REF+
REF-
RUN
HYSTERETIC
COMPARATOR
CURRENT
LIMIT
LOWER
LIMIT
V
O
HMI
R1
R2
FIGURE 5. SIMPLIFIED DIAGRAM OF OUTPUT VOLTAGE
REGULATION AND MODE SWITCHING
FB
PEAK-CURRENT
CONTROL LOOP
HIP5020
HIP5020
相關PDF資料 |
PDF描述 |
|---|---|
| HIP5020DB | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5060 | () |
| HIP5061 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5061DS | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HIP5020DB | 制造商:Rochester Electronics LLC 功能描述:SYNCHRONOUS BUCK -28 SOIC -0-70C - Bulk |
| HIP5020DB WAF | 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述: |
| HIP5020EVAL2 | 制造商:Harris Corporation 功能描述: |
| HIP5060 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip PowerSupply |
| HIP5060D WAF | 制造商:Harris Corporation 功能描述: |
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