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參數(shù)資料
| 型號(hào)： | HIP4084AP |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | 40000 SYSTEM GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 1.7 A 4 CHANNEL, FULL BRDG BASED MOSFET DRIVER, PDIP28 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 639K |
| 代理商： | HIP4084AP |
4
Peak Pulse Pulldown Current
V
OUT
12V to 4V
0.7
1.1
1.5
0.5
1.7
A
Switching Specifications
V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 10K, Gate Capacitance (C
GATE
) = 1000pF
PARAMETER
TEST CONDITIONS
T
J
= 25
o
C
T
J
= -40
o
C TO
150
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
TURN ON DELAY AND PROPAGATION DELAY
Dead Time
R
DEL
= 100K
3.8
4.5
6
3
7
μ
s
R
DEL
= 10K
0.38
0.5
0.65
0.3
0.7
μ
s
Dead Time Channel Matching
R
DEL
= 10K
-
7
15
-
20
%
Lower Turn-Off Propagation Delay
(xLI-xLO)
No Load
-
25
50
-
70
ns
Upper Turn-Off Propagation Delay
(xHI-xHO)
No Load
-
55
80
-
100
ns
Lower Turn-On Propagation Delay
(xLI-xLO)
No Load
-
40
85
-
100
ns
Upper Turn-On Propagation Delay
(xHI-xHO)
No Load
-
75
110
-
150
ns
Rise Time
C
GATE
= 1000pF
-
20
40
-
50
ns
Fall Time
C
GATE
= 1000pF
-
10
20
-
25
ns
Turn-On Input Pulse Width
50
-
-
50
-
ns
Turn-Off Input Pulse Width
50
-
-
50
-
ns
Disable (EN) Turn-Off Propagation Delay
(EN - xLO)
-
50
80
90
ns
Disable (EN) Turn-Off Propagation Delay
(EN - xHO)
-
75
100
-
125
ns
Enable to Lower Turn-On Propagation Delay
(EN - xLO)
-
50
80
-
100
ns
Enable to Upper Turn-On Propagation Delay
(EN- xHO)
R
DEL
= 10K
-
1.2
2
-
3
μ
s
Refresh Pulse Width (xLO)
375
580
900
350
950
μ
s
Electrical Specifications
V
DD
= V
xHB
= 12V, V
SS
= V
xHS
= 0V, R
DEL
= 20K, UVLO/EN =
∞
, Gate Capacitance (C
GATE
) = 1000pF
PARAMETER
TEST CONDITIONS
T
J
= 25
o
C
T
J
= -40
o
C TO
150
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
HIP4084
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