參數(shù)資料
型號(hào): HIP4084
廠商: Intersil Corporation
英文描述: 40000 SYSTEM GATE LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN
中文描述: 80V的,四相驅(qū)動(dòng)0.50A
文件頁(yè)數(shù): 2/6頁(yè)
文件大?。?/td> 639K
代理商: HIP4084
2
TRUTH TABLE
INPUT
OUTPUT
ALI, BLI, CLI, DLI
AHI, BHI, CHI, DHI
UVLO/EN
R
DEL
X
ALO, BLO,
CLO, DLO
AHO, BHO,
CHO, DHO
X
X
0
0
0
1
X
1
>100mV
1
0
0
0
1
X
0
1
0
1
1
X
0
0
1
0
1
<100mV
1
1
NOTE: X signifies that input can be either a “1” or “0”.
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
2
27
17
14
AHB
BHB
CHB
DHB
(xHB)
High-side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect
cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.
3
5
10
12
AHI
BHI
CHI
DHI
(xHI)
High-Side Logic Level Inputs. Logic at these three pins controls the three high-side output drivers, AHO (Pin 1),
BHO (Pin 26) and CHO (Pin 18) and DHO (Pin 15). When xHI is low, xHO is high. When xHI is high, xHO is low.
Unless the dead time is disabled by connecting R
DEL
(Pin 8) to ground, the low side input of each phase will
override the corresponding high side input on that phase. If R
DEL
is tied to ground, dead time is disabled and
the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. EN (Pin 9) also over-
rides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than V
DD
). An internal
100
μ
A pull-up to V
DD
will hold each xHI high if the pins are not driven.
Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output drivers ALO (Pin 24),
BLO (Pin 23) and CLO (Pin 21) and DLO (Pin 20). If the upper inputs are grounded then the lower inputs controls
both xLO and xHO drivers, with the dead time set by the resistor at R
DEL
(Pin 8). EN (Pin 9) high level input
overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than V
DD
). An
internal 100
μ
A pull-up to V
DD
will hold xLI high if these pins are not driven.
Ground. Connect the sources of the low-side power MOSFETs to this pin.
4
6
11
13
ALI
BLI
CLI
DLI
(xLI)
7
V
SS
R
DEL
8
Dead Time Setting. Connect resistor from this pin to V
DD
to set timing current that defines the dead time be-
tween drivers. All drivers turn-off with no adjustable delay, so the R
DEL
resistor guarantees no shoot-through by
delaying the turn-on of all drivers. When R
DEL
is tied to V
SS
, both upper and lowers can be commanded on
simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1
μ
F or smaller may be
connected between R
DEL
and V
SS
.
A resistor can be connected between this pin and V
SS
to program the under voltage set point. With this pin not
connected the undervoltage setpoint is typically 6.6V. When this pin is tied to V
DD
, the undervoltage setpoint is
typically 6.2V. With this pin tied to V
SS
, all six outputs are taken low, overriding all other inputs.
High-Side Outputs. Connect the gates of the high-side power MOSFETs to these pins.
9
RUV/EN
1
26
18
15
AHO
BHO
CHO
DHO
(xHO)
28
25
19
16
AHS
BHS
CHS
DHS
(xHS)
High-Side Source connection. Connect the sources of the high-side power MOSFETs to these pins. The nega-
tive side of the bootstrap capacitors should also be connected to these pins.
22
V
DD
ALO
BLO
CLO
DLO
(xLO)
Positive supply. De-couple this pin to V
SS
(Pin 7).
Low-Side Outputs. Connect the gates of the low-side power MOSFETs to these pins.
24
23
21
20
NOTE: x = A, B, C and D
HIP4084
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