- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385381 > HIP2030 (Intersil Corporation) 30V MCT/IGBT Gate Driver(MOS可控硅晶體管/絕緣柵雙極晶體管門驅(qū)動(dòng)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | HIP2030 |
| 廠商： | Intersil Corporation |
| 英文描述： | 30V MCT/IGBT Gate Driver(MOS可控硅晶體管/絕緣柵雙極晶體管門驅(qū)動(dòng)器) |
| 中文描述： | 30V的海運(yùn)碼頭/ IGBT柵極驅(qū)動(dòng)器（馬鞍山可控硅晶體管/絕緣柵雙極晶體管門驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 94K |
| 代理商： | HIP2030 |
5
HIP2030
20
CLMP
An internal 12V clamp that can be used for additional regulation across P0 (Pin 22) and P- (Pin 16).
21
POS
Positive supply rail for the charge pump.
22
P0
Chip positive supply. This pin is generally used as the DC bias power supply positive input.
23
GO
Main channel output (Gate Output). The gate output controls the switching of power devices and is normally
connected to the P-MCT gate. GO can sink or source greater than 6A peak at VP+ equal to 30V.
24
AO
A-Channel Output. AO has a CMOS output that switches from P0 (Pin 22) to P- (Pin 16). AO can source or sink
10mA of DC current.
25
BO
B-Channel Output. B-channel has a PMOS output that connects BO to P0 (Pin 22) when turned on. BO can
source 10mA of DC current from P0.
26
LO
L-Channel Output. L-channel has a NMOS output that connects LO to P- (Pin 16) in latch mode. LO can sink
10mA of DC current.
27
NC
Unused pin.
28
P+
High side output. Connects to the output of a charge pump steering diode. A 10.0
μ
F capacitor is normally con-
nected from this output to P0 (Pin 22) to supply the high side of the gate voltage.
Pin Descriptions
(Continued)
PIN
NUMBER
SYMBOL
DESCRIPTION
HIP2030 Application Information
The
Intersil Photo-Coupled Isolated Gate Drive
(HPCIGD)
circuit, illustrated in Figure 3, contains four subcircuits: a Single
Supply DC bias, a Regulated voltage divider reference, a Local
Energy Source Capacitance, and a Photo-Couple Receiver.
The
Single Supply DC Bias Circuit
, shown in Figure 3, con-
sists of a single external dropping resistor (R1) connected
between pins P+ (U1-28) and P0 (U1-22). When an input volt-
age of 30V is applied across pins P+ and P- (U1-16), R1 forms
a resistive divider network with the input impedance located
between pins P0 and P- (RVP0). This allows the circuit
designer to adjust the value of R1 to obtain a desired bias volt-
age between pins P0 and P- (VP0.). The value of RVP0 can be
calculated by evaluating the equivalent Quiescent Input Imped-
ance (RQ) and the 5V reference impedance (RR) as parallel
resistances. The values for R1, RQ, RR, and RVP0 can be
determined by using Equations 1(A, B, C, D) as shown in
Appendix A, Exercise 1.1.
The
Regulated Voltage Divider Reference
is comprised of
two resistors (R3 and R4) connected in series and are located
across pins P0 and REG. This voltage divider provides a stable
voltage reference to all of the HIP2030 comparator inputs.
Resistors R3 and R4 are selected equal in value to create a
midpoint bias reference between the peak to peak input signal
of U2. Also, the midpoint bias method ensures that input signals
generated from U2 and midpoint bias reference voltages are
within a safe common mode voltage range of the comparators.
The
Local Energy Source Capacitances
, C1 and C2, are
needed to supply the charge required to drive large capaci-
tance loads at high dv/dts. The HPCIGD circuit uses low cost
“oversized” tantalum capacitors (C = 10
μ
F) that are used for C1
and C2. If rise times and overshoot are critical, ceramic capaci-
tors with low ESL and ESR should be used to improve gate
drive signals. In a power circuit, where the gate driver is
exposed to high dv/dts, the network of C1 and C2 directs noise
current away from the HIP2030. This allows the HFOIGD circuit
to operate well in half bridge power circuits that use a trans-
former coupled power source.
The
Photo-Coupled Receiver
subcircuit consists of U2, R5, C4,
and R6. U2 is a photocoupler which combines an infrared emitter
diode (IRED) and a high speed photo detector to translate light
pulses to low voltage input signals. These signals are routed to
the G channel and are used to control the output GO. Compo-
nent R5 is used to limit the DC current through the IRED when
the input signal voltage switches to its most positive level. A wide
range of input voltages may be accommodated by varying R5 to
limit the IRED current to 25mA. C4 is a speed up capacitor andis
selected to match the forward bias capacitance of the IR diode.
The last component, R6, is an optional part and is intended to be
a termination resistor with the value set by the user.
The Intersil HIP2030 Evaluation Board (HIP2030EVAL) is a
printed circuit board (PCB) developed to help evaluate the
performance of the HIP2030 MCT/IGBT Driver IC in power
switching circuits. The component layout of the HIP2030DB
circuit enables the user to conveniently populate the PCB for
either Photo-Coupled or fiber-optic receivers. In addition, the
PCB layout has provisions for “on board prototyping” and spe-
cial function components. This facilitates the gate drive circuit
design and allows the user to exercise the internal architec-
ture and special functions of the HIP2030. The schematic of
the HIP2030DB, illustrated in Figure 4, uses the basic
HPCIGD circuitry and has provisions for “on board prototyp-
ing” and special function components.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP2100IB | 100V/2A Peak, Low Cost, High Frequency Half Bridge Driver |
| HIP5015EVAL2 | () |
| HIP5060DW | Power Control IC Single Chip PowerSupply |
| HIP5060DY | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6003 | Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP2030B4 WAF | 制造商:Harris Corporation 功能描述: |
| HIP2030EVAL | 制造商:Harris Corporation 功能描述: |
| HIP2060 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:60V, 10A Half Bridge Power MOSFET Array |
| HIP2060 WAF | 制造商:Intersil Corporation 功能描述: |
| HIP2060AS1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:60V, 10A Half Bridge Power MOSFET Array |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。