參數(shù)資料
型號(hào): HIN236
廠商: HARRIS SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: 5V Powered RS-232 Transmitters/Receivers(正5V電源電壓、RS-232收發(fā)器)
中文描述: LINE TRANSCEIVER
文件頁(yè)數(shù): 10/20頁(yè)
文件大?。?/td> 626K
代理商: HIN236
10
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic threshold
is about 26% of V
CC
, or 1.3V for V
CC
= 5V. A logic 1 at the
input results in a voltage of between -5V and V- at the output,
and a logic 0 results in a voltage between +5V and (V+ -0.6V).
Each transmitter input has an internal 400k
pullup resistor so
any unused input can be left unconnected and its output
remains in its low state. The output voltage swing meets the
RS-232C specifications of
±
5V minimum with the worst case
conditions of: all transmitters driving 3k
minimum load
impedance, V
CC
= 4.5V, and maximum allowable operating
temperature. The transmitters have an internally limited output
slew rate which is less than 30V/
μ
s. The outputs are short
circuit protected and can be shorted to ground indefinitely. The
powered down output impedance is a minimum of 300
with
±
2V applied to the outputs and V
CC
= 0V.
Receivers
The receiver inputs accept up to
±
30V while presenting the
required 3k
to 7k
input impedance even if the power is off
(V
CC
= 0V). The receivers have a typical input threshold of
1.3V which is within the
±
3V limits, known as the transition
region, of the RS-232 specifications. The receiver output is
0V to V
CC
. The output will be low whenever the input is
greater than 2.4V and high whenever the input is floating or
driven between +0.8V and -30V. The receivers feature 0.5V
hysteresis to improve noise rejection. The receiver Enable
line EN, when set to logic “1”, (HIN236, 239, 240, and 241)
disables the receiver outputs, placing them in the high
impedance mode. The receiver outputs are also placed in
the high impedance state when in shutdown mode.
T
OUT
V- < V
TOUT
< V+
300
400k
T
XIN
GND < T
XIN
< V
CC
V-
V+
V
CC
FIGURE 2. TRANSMITTER
R
OUT
GND < V
ROUT
< V
CC
5k
R
XIN
-30V < R
XIN
< +30V
GND
V
CC
FIGURE 3. RECEIVER
T
IN
OR
R
IN
V
OL
V
OL
t
PLH
t
PHL
Average Propagation Delay =t
PHL +
t
PLH
2
T
OUT
OR
R
OUT
FIGURE 4. PROPAGATION DELAY DEFINITION
HIN232, HIN236, HIN237, HIN238, HIN239, HIN240, HIN241
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