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參數(shù)資料
| 型號： | HI7191IP |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 標準包裝： | 18 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
20
FN4138.8
June 1, 2006
Control Register
The Control Register contains 24-bits to control the various
sections of the HI7191. This register is a read/write register.
DC - Bit 23 is the Data Coding Bit used to select between
two’s complementary and offset binary data coding. When
this bit is set (DC = 1) the data in the Data Output Register
will be two’s complement. When cleared (DC = 0) this data
will be offset binary. When operating in the unipolar mode
the output data is available in straight binary only (the DC bit
is ignored). This bit is cleared after a RESET is applied to the
part.
FP10 through FP0 - Bits 22 through 12 are the Filter
programming bits that determine the frequency response of
the digital filter. These bits determine the filter cutoff
frequency, the position of the first notch and the data rate of
the HI7191. The first notch of the filter is equal to the
decimation rate and can be determined by the formula:
fNOTCH = fOSC /(512 x CODE)
where CODE is the decimal equivalent of the value in FP10
through FP0. The values that can be programmed into these
bits are 10 to 2047 decimal, which allows a conversion rate
range of 9.54Hz to 1.953kHz when using a 10MHz clock.
Changing the filter notch frequency, as well as the selected
gain, impacts resolution. The output data rate (or effective
conversion time) for the device is equal to the frequency
selected for the first notch to the filter. For example, if the
first notch of the filter is selected at 50Hz then a new word is
available at a 50Hz rate or every 20ms. If the first notch is at
1kHz a new word is available every 1ms.
The settling-time of the converter to a full scale step input
change is between 3 and 4 times the data rate. For example,
with the first filter notch at 50Hz, the worst case settling time
to a full scale step input change is 80ms. If the first notch is
1kHz, the settling time to a full scale input step is 4ms
maximum.
The -3dB frequency is determined by the programmed first
notch frequency according to the relationship:
f -3dB = 0.262 x fNOTCH.
MD2 through MD0 - Bits 11 through 9 are the Operational
Modes of the converter. See Table 4 for the Operational
Modes description. After a RESET is applied to the part
these bits are set to the self calibration mode.
B/U - Bit 8 is the Bipolar/Unipolar select bit. When this bit is
set the HI7191 is configured for bipolar operation. When this
bit is reset the part is in unipolar mode. This bit is set after a
RESET is applied to the part.
FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW
FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH
THREE-STATE
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I
7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14
B15
THREE-STATE
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I
7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14
B15
BYTE 2
MSB
22212019181716
DC
FP10
FP9
FP8
FP7
FP6
FP5
FP4
BYTE 1
15
14
13
12
11
10
9
8
FP3
FP2
FP1
FP0
MD2
MD1
MD0
B/U
BYTE 0
7654321
LSB
G2
G1
G0
BO
SB
BD
MSB
SDL
HI7191
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