參數(shù)資料
| 型號： | HI7190IP |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 標準包裝： | 18 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
12
FN3612.10
June 27, 2006
AVDD - 1.8V. Exceeding this range on the VCM pin will
compromise the device performance.
Transducer Burn-Out Current Source
The VINHI input of the HI7190 contains a 500nA (Typ) current
source which can be turned on/off via the Control Register.
This current source can be used in checking whether a
transducer has burnt-out or become open before attempting
to take measurements on that channel. When the current
source is turned on an additional offset will be created
indicating the presence of a transducer. The current source is
controlled by the BO bit (Bit 4) in the Control Register and is
disabled on power up. See Figure 7 for an applications circuit.
Digital Section Description
A block diagram of the digital section of the HI7190 is shown
in Figure 8. This section includes a low pass decimation
filter, conversion controller, calibration logic, serial interface,
and clock generator.
Digital Filtering
One advantage of digital filtering is that it occurs after the
conversion process and can remove noise introduced during
the conversion. It can not, however, remove noise present
on the analog signal prior to the ADC (which an analog filter
can).
One problem with the modulator/digital filter combination is
that excursions outside the full scale range of the device
could cause the modulator and digital filter to saturate. This
device has headroom built in to the modulator and digital
filter which tolerates signal deviations up to 33% outside of
the full scale range of the device. If noise spikes can drive
the input signal outside of this extended range, it is
recommended that an input analog filter is used or the
overall input signal level is reduced.
Low Pass Decimation Filter
The digital low-pass filter is a Hogenauer (sinc) decimating
filter. This filter was chosen because it is a cost effective low
pass decimating filter that minimizes the need for internal
multipliers and extensive storage and is most effective when
used with high sampling or oversampling rates. Figure 9
shows the frequency characteristics of the filter where fC is
the -3dB frequency of the input signal and fN is the
programmed notch frequency. The analog modulator sends
a one bit data stream to the filter at a rate of that is
determined by:
fMODULATOR = fOSC/128
fMODULATOR = 78.125kHz for fOSC = 10MHz.
The filter then converts the serial modulator data into 40-bit
words for processing by the Hogenauer filter. The data is
decimated in the filter at a rate determined by the CODE
word FP10-FP0 (programed by the user into the Control
Register) and the external clock rate. The equation is:
fNOTCH = fOSC/(512 x CODE).
The Control Register has 11 bits that select the filter cutoff
frequency and the first notch of the filter. The output data
update rate is equal to the notch frequency. The notch
frequency sets the Nyquist sampling rate of the device while
the -3dB point of the filter determines the frequency
spectrum of interest (fS). The FP bits have a usable range of
10 through 2047 where 10 yields a 1.953kHz Nyquist rate.
The Hogenauer filter contains alias components that reflect
around the notch frequency. If the spectrum of the frequency
of interest reaches the alias component, the data has been
aliased and therefore undersampled.
Filter Characteristics
Please note: We have recently discovered a
performance anomaly with the HI7190. The problem
occurs when the digital code for the notch filter is
programmed within certain frequencies. We believe the
error is caused by the calibration logic and the digital
notch code NOT the absolute frequency. The error is
seen when the user applies mid-scale (0V input, Bipolar
mode). With this input, the expected digital output
VRHI
VRLO
VINHI
VINLO
AVDD
AVSS
CURRENT
SOURCE
HI7190
RATIOMETRIC
CONFIGURATION
LOAD CELL
FIGURE 7. BURN-OUT CURRENT SOURCE CIRCUIT
MODULA
T
OR
OUTP
U
T
SERIAL I/O
SDO
SDIO
SCLK
CS
DRDY
RESET
SYNC
OSC2
OSC1
MODULATOR
CLOCK
DIGITAL
CALIBRATION
AND CONTROL
CLOCK
GENERATOR
FILTER
FIGURE 8. DIGITAL SECTION BLOCK DIAGRAM
HI7190
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| HI7191IB | 功能描述:IC ADC 24BIT PROGBL SER 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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