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參數(shù)資料
| 型號(hào)： | HI2559JCQ |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | 1-Bit D/A Converter For Audio Application |
| 中文描述： | SERIAL INPUT LOADING, 1-BIT DAC, PQFP32 |
| 封裝： | MQFP-32 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 669K |
| 代理商： | HI2559JCQ |
4-2
Block Diagram
DIGITAL
FILTER
(OVER SAMPLING)
CLOCK GENERATOR
TIMING CIRCUIT
LRCK
BCK
SIN
MASL
MLSL
ATT
SHIFT
LATCH
S
P
HOST
COMPUTER
I/F
XTLI
XTLO
XCLK
DAC1
DAC2
AOUT1 (+)
AOUT1 (-)
AOUT2 (+)
AOUT2 (-)
ROM
ATT1
ATT2
RAM
Pin Descriptions
PIN NO.
SYMBOL
I/O
DESCRIPTION
1
AV
DD0
-
Analog power supply for Channel 2 output.
2
AOUT2(–)
O
Analog reversed phase output for Channel 2.
3
ADV
SS0
-
Analog GND for Channel 2 output.
4
DV
DD0
-
Digital power supply.
5
TEST
I
IC measurement. Fixed to Low.
6
CLR
I
System clear input. Cleared when low. Equipped with a pull-up resistor.
7
MASL
I
Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the
serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low.
Equipped with a pulldown resistor.
8
DV
SS0
-
Digital GND.
9
LRCK
I
Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data
when low.
10
BCK
I
Serial bit transfer clock 48 F
S
or 64 F
S
in serial IN. The serial input data is retrieved at the
rising edge.
11
SIN
I
Two channels per sampling serial data input. Data format is represented by 2’s comple-
ments, and consists of 24-bit or 32-bit slots.
12
MLSL
I
Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSB-
first when High; LSB-first when Low. Equipped with a pull-up resistor.
HI2559, CXD2559
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