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參數資料
| 型號： | HI20206JCP |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | Triple 8-Bit, 35 MSPS, RGB, 3-Channel D/A Converter |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.016 us SETTLING TIME, 8-BIT DAC, PDIP42 |
| 封裝： | PLASTIC, DIP-42 |
| 文件頁數： | 11/13頁 |
| 文件大?。?/td> | 171K |
| 代理商： | HI20206JCP |
10-11
(2)
Phase Relationship Between Data and Clock
In order to obtain the desired characteristics as a D/A
converter, it is necessary to set the phase relationship
correctly between the externally applied data and
clock.
Satisfy the standard of the set-up time (t
S
) and hold
time (t
H
) indicated in the electrical characteristics. As to
the meaning of t
S
and t
H
, see the timing chart.
Moreover, the clock pulse width is desired to be as
indicated in the recommended operating condition.
(3)
Regarding the Load of D/A Output Pin
Receive the D/A output of the next stage with high
impedance. In other words perform so that it becomes
as follows:
R
L
> 10k
C
L
< 20pF.
The temperature characteristics indicated in the
characteristics diagram has been measured under this
condition.
However, when it is made R
L
≤
10k
the temperature
characteristics may change considerably. In addition,
when it is made to C
L
≥
20pF, the rise and fall of the
D/A output become slow and will not operate at high
speed.
(4)
Noise Reduction Measures
As the D/A output voltage is a minute voltage of
approximately 4mV per one step, ingenuity is required
in reducing the noise entering from the outside of the
IC as much as possible. Therefore, use the items given
below as reference.
When mounting onto the printed board, allow as
much space as possible to the ground surface and
the V
CC
surface on the board and reduce the para-
sitic inductance and resistance.
It is desirable that the AGND and DGND be sepa-
rated in the pattern on the board. It is similar with
AV
CC
and DV
CC
. As shown in the diagram below, for
example, it is recommended that the wiring to the
electric supply of AGND and DGND as also AV
CC
and DV
CC
be conducted separately, and then mak-
ing AGND and DGND as also AV
CC
and DV
CC
in
common right near the power supply respectively.
Insert in parallel a 47
μ
F tantalum capacitor and a
100pF ceramic capacitor between the V
CC
surface
on the printed board and the nearmost ground sur-
face. (A of diagram below). It is also desirable to
insert the above between the V
CC
surface near the
pin of the IC and the ground surface (see Figure 11).
They are bypass capacitors to prevent bad effects
from occurring to the characteristics when the power
supply voltage fluctuates due to the clock, etc.
It is recommended to reduce noise which overlaps
the D/A output by inserting a capacitor of over 0.1
μ
F
between pin 25 (AGND) and pin 26 (V
SET
).
PRINTED BOARD
HI20206
POWER SUPPLY
+
0
DGND
AGND
AV
CC
DV
CC
A
B
FIGURE 11.
HI20206
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