參數(shù)資料
型號(hào): HI-8582
廠商: Holt Integrated Circuits
英文描述: 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
中文描述: ARINC公司429片上系統(tǒng)
文件頁數(shù): 6/15頁
文件大?。?/td> 419K
代理商: HI-8582
READINGLABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (
used to read labels for receiver 1, and
receiver2. LabeldataispresentedonDB0-DB7.
taken low) are labels.
EN2
is
to read labels for
Whenwritingto,orreadingfromthelabelmemory,SELmustbea
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
EN
EN1
TRANSMITTER
FIFOOPERATION
TheFIFOisloaded sequentiallybyfirstpulsing
andthen
toloadbyte2. Thecontrollogicautomaticallyloads
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
beloaded. IfTX/Rislow,thenonlytheavailablepositionsmaybe
loaded. Ifall32positionsarefull,the
FIFOignoresfurtherattemptstoloaddata.
toloadbyte1
flagisassertedandthe
A transmitter FIFO half-full flag
transmit FIFO contains less than 16 words,
indicating to the system microprocessor that a 16 ARINC word
blockwritesequencecanbeinitiated.
is provided. When the
HFT
is high,
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If CR4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treatedasdataandaretransmitted.
PL1
PL2
FFT
HFT
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00-BD07 are
alwayscomparedtoreceivedARINCbits1-8respectively.
After a write that takes CR1 from 0 to 1, the next 16 writes of data
(
pulsed low) load label data into each location of the label
memory from the BD0-7 pins. The
data for receiver 1 and
for receiver 2.
PL2
receptionissuspendedduringthelabelmemorywritesequence.
pin is used to write label
Note that ARINC word
LOADINGLABELS
PL
PL1
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1",
will go low. The data flag for a receiver will remain low until
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating
byte selector, low to retrieve the first byte and then activating
with SEL high to retrieve the second byte.
fromreceiver1and
retrievesdatafromreceiver2.
EN2
or
(or both)
both
with SEL, the
retrieves data
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The
(
) pin will go lowwhen the receiver 1 (2) FIFOis full.
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag
contains16ormorereceivedARINCwords.The
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the HI-
8582’sstatusregisterbits.
(
) goes low if the FIFO
(
HF1 HF2
)pinis
D/R1
D/R2
EN
EN
EN1
FF1 FF2
HF1 HF2
LABELRECOGNITION
HI-8582, HI-8583
HOLT INTEGRATED CIRCUITS
6
相關(guān)PDF資料
PDF描述
HI-8582PQI 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
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HI-8583PQT ARINC 429 SYSTEM ON A CHIP
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