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參數(shù)資料
| 型號(hào)： | HI-8582 |
| 廠商： | Holt Integrated Circuits |
| 英文描述： | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | ARINC公司429片上系統(tǒng) |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大小： | 419K |
| 代理商： | HI-8582 |
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SIGNAL
VDD
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
HF1
D/R2
FF2
HF2
FUNCTION
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
DESCRIPTION
+5V ± %
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
FIFO Half full, Receiver 1
Receiver 2 data ready flag
FIFO full Receiver 2
FIFO Half full, Receiver 2
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0 V
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
I/O
I/O
I/O
I/O
I/O
I/O
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Transmitter FIFO Half Full
Transmitter FIFO Full
-9.5V to -12.6V
Line driver output - A side
Line driver output - B side
+9.5V to +12.6V
Enable Transmission
Clock for control word register
Read Status Register if SEL=0, read Control Register if SEL=1
No frequency discrimination if low (pull-up)
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
Disable Transmitter output if high (pull-down)
SEL
EN1
EN2
is high
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
INPUT
INPUT
OUTPUT
TX/R
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
V-
TXAOUT
TXBOUT
V+
ENTX
CWSTR
RSR
NFD
CLK
TX CLK
MR
TEST
EN1
PL1.
HFT
FFT
PIN DESCRIPTIONS
HI-8582, HI-8583
HOLT INTEGRATED CIRCUITS
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8582PQI | 384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI-8582PQT | ARINC 429 SYSTEM ON A CHIP |
| HI-8583 | ARINC 429 SYSTEM ON A CHIP |
| HI-8583PQI | ARINC 429 SYSTEM ON A CHIP |
| HI-8583PQT | ARINC 429 SYSTEM ON A CHIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8582_06 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
| HI-8582_13 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
| HI-8582CJI | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJI-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 SYSTEM ON A CHIP |
| HI-8582CJIF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:ARINC 429 System on a Chip |
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