
6
The DATA/DATA differential stage is not a factor for the
speed if its current sources have enough current not to
bottleneck the transient. However it should be noted that the
propagation delay mismatch is determined by this stage.
Sufficient current is allocated to the differential stage current
sources to best match the low-to-high and high-to-low
transient propagation delays.
Figure 3 shows various output responses, 0V to 1V, 0V to 3V,
0V to 5V, and -2V to 7V (full swing). The load condition is a 16
inch 50
SMA cable with a 5pF capacitor at the end of the
cable. The rise/fall time with 5V
P-P
is typically 1.45ns for the
HFA5251. Pin drivers, built out of the same circuit structure as
shown in Figure 2, can be made faster by trimming for a
higher power supply current. Currently the pin driver has
rise/fall times of less than 1ns (10% to 90% of 5V
P-P
) when
I
CC
is trimmed to 125mA. Further speed enhancement will be
made if there is a market demand.
Basic ATE System Application
Figure 3 shows a pin driver in a typical per-pin ATE system.
The pin driver works closely with the dual-level comparator
and the active load. When the DUT pin acts as an input
waiting for a series of digital signals, the pin driver becomes
active with a logic “0” applied on the HiZ pin and provides the
DUT pin with digital signals. When the DUT pin acts as an
output, the pin driver output will be in high impedance mode
(HiZ) with a logic “1” applied to the “HiZ” pin of the pin driver.
During this high impedance mode the pin driver presents a
capacitance of less than 5pF to the DUT. Special care has to
be taken to match the impedance (to 50
) at the pin driver
output to minimize reflections.
The dual level comparator detects the logic levels of the DUT
pin when it acts as an output. The comparator has two
threshold level inputs, VCH and VCL. The logic level
information of DUT pin output is sent to the edge/window
comparator through the dual level comparator. The
edge/window comparator interprets this information in terms
of corresponding transient performance in conjunction with
the timing information. Thus it detects any possible failure
transients.
V
CC1
V
EE1
DATA
DATA
V
HIGH
V
LOW
VSO
V
OUT
HIZ
HIZ
V
CC2
V
EE2
HIZ CONTROL
OUTPUT STAGE
SWITCHING STAGE
V
HIGH
/V
LOW
CONTROL
FIGURE 2. CIRCUIT SCHEMATIC
411ns
2ns/DIV.
431ns
7V
5V
3V
1V
0V
-2V
2.2V/DIV.
FIGURE 3. OUTPUT RESPONSE WITH VARIOUS V
LOW
AND
V
HIGH
CONDITIONS
HFA5251