參數(shù)資料
型號(hào): HFA3861BIN
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): 無(wú)繩電話(huà)/電話(huà)
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封裝: 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64
文件頁(yè)數(shù): 25/36頁(yè)
文件大?。?/td> 733K
代理商: HFA3861BIN
25
Bit 1
I A/D clock
0 = enable
1 = disable
Bit 0
Q A/D clock
0 = enable
1 = disable
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued)
CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2
Bit 7
Standby
1 = enable
0 = disable
Bit 6
SLEEPTX
1 = enable
0 = disable
Bit 5
SLEEP RX
1 = enable
0 = disable
Bit 4
SLEEP IQ
1 = enable
0 = disable
Bit 3
Analog TX Shut_down
1 = enable
0 = disable
Bit 2
Analog RX Shut_down
1 = enable
0 = disable
Bit 1
Analog Standby
1 = enable
0 = disable
Bit 0
Enable manual control of mixed signal power down signals using bits 1:7
1 = enable
0 = disable, normal operation (devices controlled by RESET, TX_PE, RX_PE)
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3
Bit 7
DFS - select straight binary output of I/Q and RF A/D converters
Bits 6:4
I/Q DAC input control. This DAC gives an analog look at various internal digital signals that are suitable for analog
representation.
000 = normal (TX filter)
001 = down converter
010 = E/L integrator - upper 6 bits (Q) and AGC error (I)
011 = I/ Q A/D’s
100 = Bigger picker output. Upper 6 bits of FWT_I winner and FWT_Q winner
101 = CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved
between them
110 = Test Bus pins (5:0) when configured as inputs, CR32(4), to both I and Q inputs
111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32
Bit 3
Enable test bus into RX and TX DAC (if below bit is 0)
0 = normal
1 = enable
Bit 2
Enable RF A/D into RX DAC
0 = normal
1 = enable
Bit 1
VRbit1
Bit 0
VRbit0
HFA3861B
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