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參數(shù)資料
| 型號： | HFA3861B |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴譜基帶處理器) |
| 中文描述： | 直接序列擴頻基帶處理器（直接序列擴譜基帶處理器） |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HFA3861B |
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13
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period, when this happens,
SQ1 is updated between 8 and 9
μ
s into the 10
μ
s dwell. If
CS1 is not active, two consecutive SQ1’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The receive signal strength indication (RSSI) measurement
is derived from the state of the AGC circuit. ED is the
comparison result of RSSI against a threshold. The
threshold may be set to an absolute power value, or it may
be set to be N dB above the measured noise floor. See CR
38. The HFA3861B measures and stores the RSSI level
when it detects no presence of BPSK or QPSK signals. The
smallest value of a 256 value buffer is taken to be the noise
floor. Thus, the value of the noise floor will adapt to the
environment. A separate noise floor value is maintained for
each antenna. An initial value of the noise floor is
established within 50
μ
s of the chip being active and is
refined as goes on. Deasserting RX_PE does not corrupt the
learned values. If the absolute power metric is chosen, this
threshold is normally set to between -70 and -80dBm.
If desired, ED may be used in the acquisition process as well
as CCA. ED may be used to mask (squelch) weak signals
and prevent radio reception of signals too weak to support
the high data rates, signals from adjacent cells, networks, or
buildings. See CR48.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allow CCA to be programmed to be a function of
ED only, the logical operation of (CS1 OR SQ1), the logical
function of (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR
SQ1)).
CR11(3) lets the user select from sampled CCA mode,
which means CCA will not glitch, is updated once per
symbol and is valid for reading at 15.8
μ
s or 19.8
μ
s. In non-
sampled mode, CCA may change at anytime, potentially
several times per slot, as ED and CS1 operate
asynchronously to slot times.
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. CCA can be programmed to be
stable to allow asynchronous sampling or even falling edge
detection of CCA. Once MD_RDY goes active, CCA is then
ignored for the remainder of the message. Failure to monitor
CCA until MD_RDY goes active (or use of a time-out circuit)
could result in a stalled system as it is possible for the
channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter, the IF to baseband
converter, and the baseband processor. The AGC loop is
digitally controlled by the BBP. Basically it operates as
follows:
Initially, the radio is set for high gain. The percent of time that
the A/D converters in the baseband processor are saturated
is monitored along with signal amplitude and the gain is
adjusted down until the amplitude is what will optimize the
demodulator’s performance. If the amount of saturation is
great, the initial gain adjust steps are large. If the signal
overload is small, they are less. When the gain is right and
the A/Ds’ outputs are within the lock window, the BBP
declares AGC lock and stops adjusting for the duration of the
packet. If the signal level then varies more than a preset
amount, the AGC is declared unlocked and the gain again
allowed to readjust.
The BBP looks for the locked state following an unlocked
state as one indication that a received signal is on the
antenna. This starts the receive process of looking for PN
correlation. Once PN correlation and AGC lock are found,
the processor begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation. This
improves the receiver dynamic range.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, or CCK symbols. The demodulator
includes a frequency tracking loop that tracks and removes
the carrier frequency offset. In addition it tracks the symbol
timing, and differentially decodes (where appropriate) and
descrambles the data. The data is output through the RX
Port to the external processor.
The PRISM baseband processor, HFA3861B uses
differential demodulation for the initial acquisition portion of
the message processing and then switches to coherent
demodulation for the MPDU demodulation. The HFA3861B
is designed to achieve rapid settling of the carrier tracking
loop during acquisition. Rapid phase fluctuations are
handled with a relatively wide loop bandwidth which is then
stepped down as the packet progresses. Coherent
HFA3861B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3861 | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴頻基帶處理器) |
| HFA3861IV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 2.4GHz - 2.5GHz 250mW Power Amplifier(2.4GHz - 2.5GHz 250mW 功率放大器) |
| HFA3926 | 2.0GHz - 2.7GHz 250mW Power Amplifier(2.0GHz - 2.7GHz 250mW 功率放大器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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