參數(shù)資料
型號: HFA3724
廠商: HARRIS SEMICONDUCTOR
元件分類: 衰減器
英文描述: 400MHz Quadrature IF Modulator/Demodulator
中文描述: MODEM
文件頁數(shù): 16/24頁
文件大?。?/td> 186K
代理商: HFA3724
16
Overall Device Description
The HFA3724 is a highly integrated baseband converter for
half duplex wireless data applications. It features all the
necessary blocks for baseband modulation and
demodulation of “I” and “Q” quadrature multiplexing signals.
It targets applications using all phase shift types of
modulation (PSK) due to its hard limiting receiving front end.
Four fully independent blocks adds flexibility for numerous
applications covering a wide range of IF frequencies. A
differential design architecture, device pin out and layout
have been chosen to improve system RF properties like
common mode signal immunity (noise, crosstalk), reduce
relevant parasitics and settling times and optimize dynamic
range for low power requirements. Single power supply
requirements from 2.7V
DC
to 5.5V
DC
makes the HFA3724 a
good choice for portable transceiver designs.
The HFA3724 has a two stage integrated limiting IF amplifier
with frequency response to 400MHz. These amplifiers
exhibit a -84dbm, -3db cascaded limiting sensitivity with a
built in Receive Signal Strength Indicator (RSSI) covering
60db of dynamic range with excellent linearity. An up
conversion and down conversion pair of quadrature doubly
balanced mixers are available for “I” and “Q” baseband IF
processing. These converters are driven by an internal
quadrature LO generator which exhibits a broadband
response with excellent quadrature properties. To achieve
broadband operation, the Local Oscillator frequency input is
required to be twice the desired frequency for
modulation/demodulation. Duty cycle and signal purity
requirements for the 2X LO input using this type of
quadrature architecture are less restrictive for the HFA3724.
Ground reference input signals as low as -15dBm and
frequencies up to 900MHz (2XLO) can be used and tailored
by the user. A buffered, divide by 2, LO single ended 50
selectable output is provided for convenience of PLL
designs. The receive channel mixers “I” and “Q” quadrature
outputs have a frequency response up to 30MHz for
baseband signals and the transmit mixers are summed and
amplified to a single ended open collector output with
frequency response up to 400MHz.
Multiplexed or half duplex baseband 5th order Butterworth
low pass filters are also included in the design. The “I” and
“Q” filters address applications requiring low pass and
antialiasing filtering for external baseband threshold
comparison or simple analog to digital conversion in the
receive channel. During transmission, the filter is used for
pulse shaping or control of spectral mask.
Four filter bandwidths are programmable, (2.2MHz, 4.4MHz,
8.8MHz and 17.6MHz) via a two bit digital or hardwired control
interface. These cut off frequencies are selected for
optimization of spectrum output responses for 2.25M, 5.5M,
11M and 22M chips/sec respectively for spread spectrum
applications (These rates can also be interpreted as symbol
rates for conventional data transmission). External processing
correlators in the receive channel as in the Intersil HSP3824
baseband converter, will bring the demodulation to lower
effective data rates. As an example, the use of 11M chips/sec,
11chipBarkercodeusingthe8.8MHzlowpassfilterinaQPSK
type of modulation scheme will bring a post processed effective
data rate to 1M symbol/sec or 2M bits/sec. Likewise, the use of
a 2.4M chips/sec, 16 chip spreading code and the use of
2.2MHz filter can process an effective data rate of 150K
symbols/sec or 300K bits/sec. In addition, these filters are
continuously tunable over a
±
20% frequency range via one
external resistor. This feature gives the user the ability to
reshape the spectrum of a transmitted signal at the antenna
port which takes into account any spectral regrowth along the
transmitter chain. The modulator “I” and “Q” filter inputs accept
digital signal levels data for modulation and their phase and
gain characteristics, including I / Q matching and group delay
are well suitable for reliable data transmission. In the Receive
mode and over the full input limiting dynamic range, both low
pass filters outputs swing a 500mV
P-P
baseband signal.
Each block has its own independent power enable control for
power management and half duplex transmit/receive
operation. A stable 2V DC output and a buffered band gap
reference voltage are also provided for an external analog to
digital conversion reference.
Detailed Description
(Refer to Block Diagram)
IF Limiter
Two independent limiting amplifiers are available in the
HFA3724. Each one exhibits a broadband response to
400MHz with 45dB of gain. The low frequency response is
limited by external components because the device has no
internal coupling capacitors. The differential limiting output
swing with a 500
load is typically 200mV
P-P
at the
fundamental frequency and is temperature stable.
Both amplifiers are very stable within their passband and the
cascaded performance also exhibits very good stability for
any input source impedance. Wide bandwidth SAW filters for
spread spectrum applications or any desired source
impedance filter implementation can be used for IF filtering
before the cascaded amplifiers. The stability is remarkable
for such an integrated solution. In fact, in many applications
it is possible to remove the bypass pin capacitors with no
degradation in stability. The cascaded -1dB and -3dB input
limiting sensitivity have been characterized as -79dbm and
84dbm respectively, for a 50
single ended input at 280MHz
and with a 47MHz bandwidth interstage bandpass LC filter
(refer to Figure 23, Test Diagram). The input sensitivity is
determined to a large extent by the bandwidth of the
interstage filter and input source impedance.
The noise figure for each stage has been characterized at
6dB for a 250
single end input impedance and 9dB for a
50
input impedance. These low noise figures combined
HFA3724
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